From: Will Deacon <will.deacon@arm•com>
To: Alexander Duyck <alexander.h.duyck@redhat•com>
Cc: "linux-arch@vger•kernel.org" <linux-arch@vger•kernel.org>,
"netdev@vger•kernel.org" <netdev@vger•kernel.org>,
"linux-kernel@vger•kernel.org" <linux-kernel@vger•kernel.org>,
"mathieu.desnoyers@polymtl•ca" <mathieu.desnoyers@polymtl•ca>,
"peterz@infradead•org" <peterz@infradead•org>,
"benh@kernel•crashing.org" <benh@kernel•crashing.org>,
"heiko.carstens@de•ibm.com" <heiko.carstens@de•ibm.com>,
"mingo@kernel•org" <mingo@kernel•org>,
"mikey@neuling•org" <mikey@neuling•org>,
"linux@arm•linux.org.uk" <linux@arm•linux.org.uk>,
"donald.c.skidmore@intel•com" <donald.c.skidmore@intel•com>,
"matthew.vick@intel•com" <matthew.vick@intel•com>,
"geert@linux-m68k•org" <geert@linux-m68k•org>,
"jeffrey.t.kirsher@intel•com" <jeffrey.t.kirsher@intel•com>,
"romieu@fr•zoreil.com" <romieu@fr•zoreil.com>,
"paulmck@linux•vnet.ibm.com" <paulmck@linux•vnet.ibm.com>,
"nic_swsd@realtek•com" <nic_
Subject: Re: [PATCH v5 2/4] arch: Add lightweight memory barriers dma_rmb() and dma_wmb()
Date: Tue, 25 Nov 2014 14:01:30 +0000 [thread overview]
Message-ID: <20141125140130.GC8541@arm.com> (raw)
In-Reply-To: <20141119012400.9563.21117.stgit@ahduyck-server>
On Wed, Nov 19, 2014 at 01:24:02AM +0000, Alexander Duyck wrote:
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index 22a969c..a1c589b 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -1615,6 +1615,47 @@ There are some more advanced barrier functions:
> operations" subsection for information on where to use these.
>
>
> + (*) dma_wmb();
> + (*) dma_rmb();
> +
> + These are for use with memory based device I/O to guarantee the ordering
> + of cache coherent writes or reads with respect to other writes or reads
> + to cache coherent DMA memory.
Can you please make it crystal clear that "memory based device I/O" != MMIO?
If people get these barriers wrong, then debugging will be a nightmare.
> diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
> index c6a3e73..d2f81e6 100644
> --- a/arch/arm/include/asm/barrier.h
> +++ b/arch/arm/include/asm/barrier.h
> @@ -43,10 +43,14 @@
> #define mb() do { dsb(); outer_sync(); } while (0)
> #define rmb() dsb()
> #define wmb() do { dsb(st); outer_sync(); } while (0)
> +#define dma_rmb() dmb(osh)
> +#define dma_wmb() dmb(oshst)
> #else
> #define mb() barrier()
> #define rmb() barrier()
> #define wmb() barrier()
> +#define dma_rmb() barrier()
> +#define dma_wmb() barrier()
> #endif
>
> #ifndef CONFIG_SMP
> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
> index 6389d60..a5abb00 100644
> --- a/arch/arm64/include/asm/barrier.h
> +++ b/arch/arm64/include/asm/barrier.h
> @@ -32,6 +32,9 @@
> #define rmb() dsb(ld)
> #define wmb() dsb(st)
>
> +#define dma_rmb() dmb(oshld)
> +#define dma_wmb() dmb(oshst)
> +
> #ifndef CONFIG_SMP
> #define smp_mb() barrier()
> #define smp_rmb() barrier()
The arm/arm64 bits look fine to me.
Acked-by: Will Deacon <will.deacon@arm•com>
If we ever see platforms using Linux/dma_alloc_coherent with devices
mastering from a different outer-shareable domain that the one containing
the CPUs, then we'll need to revisit this.
Will
next prev parent reply other threads:[~2014-11-25 14:01 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-19 1:23 [PATCH v5 0/4] arch: Add lightweight memory barriers for coherent memory access Alexander Duyck
2014-11-19 1:23 ` [PATCH v5 1/4] arch: Cleanup read_barrier_depends() and comments Alexander Duyck
2014-11-19 1:24 ` [PATCH v5 2/4] arch: Add lightweight memory barriers dma_rmb() and dma_wmb() Alexander Duyck
2014-11-25 14:01 ` Will Deacon [this message]
2014-11-25 16:26 ` Alexander Duyck
2014-11-26 16:04 ` Will Deacon
2014-11-25 23:15 ` Benjamin Herrenschmidt
2014-11-19 1:24 ` [PATCH v5 3/4] r8169: Use dma_rmb() and dma_wmb() for DescOwn checks Alexander Duyck
2014-11-19 1:24 ` [PATCH v5 4/4] fm10k/igb/ixgbe: Use dma_rmb on Rx descriptor reads Alexander Duyck
2014-11-19 1:28 ` Jeff Kirsher
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20141125140130.GC8541@arm.com \
--to=will.deacon@arm$(echo .)com \
--cc=alexander.h.duyck@redhat$(echo .)com \
--cc=benh@kernel$(echo .)crashing.org \
--cc=donald.c.skidmore@intel$(echo .)com \
--cc=geert@linux-m68k$(echo .)org \
--cc=heiko.carstens@de$(echo .)ibm.com \
--cc=jeffrey.t.kirsher@intel$(echo .)com \
--cc=linux-arch@vger$(echo .)kernel.org \
--cc=linux-kernel@vger$(echo .)kernel.org \
--cc=linux@arm$(echo .)linux.org.uk \
--cc=mathieu.desnoyers@polymtl$(echo .)ca \
--cc=matthew.vick@intel$(echo .)com \
--cc=mikey@neuling$(echo .)org \
--cc=mingo@kernel$(echo .)org \
--cc=netdev@vger$(echo .)kernel.org \
--cc=paulmck@linux$(echo .)vnet.ibm.com \
--cc=peterz@infradead$(echo .)org \
--cc=romieu@fr$(echo .)zoreil.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox