Subject: Re: Optimizing instruction-cache, more packets at each stage

From: Jesper Dangaard Brouer <[email-masked]>
Date: Mon, 18 Jan 2016 18:49:48 +0100

On Mon, 18 Jan 2016 09:36:32 -0800 Tom Herbert <[email-masked]> wrote:

> On Mon, Jan 18, 2016 at 2:27 AM, Jesper Dangaard Brouer
[...]
> > Down in the driver layer (RX), I think it is too early to categorize
> > Related/Unrelated SKB's, because we want to delay touching packet-data
> > as long as possible (waiting for the prefetcher to get data into
> > cache).
> >
> Does DDIO address this?

Data Direct IO (DDIO) delivers packet-data into L3 cache, which is
great to avoid this first cache miss on data.  But not all CPUs have
this feature.  And it is difficult to deduct which CPUs support this
feature.

For test purposes, I do have systems both with and without DDIO.

I'm currently setting up as Skylake CPU based system, which I believe
don't have DDIO.  The reason for this system is that, the Skylake CPU
should have better PMU support for profiling icache and front-end.
I'll soon verify this...

-- 
Best regards,
  Jesper Dangaard Brouer
  MSc.CS, Principal Kernel Engineer at Red Hat
  Author of http://www.iptv-analyzer.org
  LinkedIn: http://www.linkedin.com/in/brouer