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From: Ido Schimmel <idosch@mellanox•com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded•com>
Cc: Jiri Pirko <jiri@resnulli•us>, <netdev@vger•kernel.org>,
	<davem@davemloft•net>, <eladr@mellanox•com>,
	<yotamg@mellanox•com>, <ogerlitz@mellanox•com>
Subject: Re: [patch net 2/2] mlxsw: pci: Correctly determine if descriptor queue is full
Date: Mon, 7 Mar 2016 16:12:34 +0200	[thread overview]
Message-ID: <20160307141234.GA15734@colbert.mtl.com> (raw)
In-Reply-To: <56DD8A8B.8000705@cogentembedded.com>

Mon, Mar 07, 2016 at 04:04:59PM IST, sergei.shtylyov@cogentembedded•com wrote:
>Hello.
>
>On 3/7/2016 11:24 AM, Jiri Pirko wrote:
>
>> From: Ido Schimmel <idosch@mellanox•com>
>>
>> The descriptor queues for sending (SDQs) and receiving (RDQs) packets
>> are managed by two counters - producer and consumer - which are both
>> 16-bit in size. A queue is considered full when the difference between
>> the two equals the queue's maximum number of descriptors.
>>
>> However, if the producer counter overflows, then it's possible for the
>> full queue check to fail, as it doesn't take the overflow into account.
>> In such a case, descriptors already passed to the device - but for which
>> a completion has yet to be posted - will be overwritten, thereby causing
>> undefined behavior. The above can be achieved under heavy load (~30
>> netperf instances).
>>
>> Fix that by casting the substraction result to u16, preventing it from
>
>    Subtraction.

Will fix that in v2.

Thanks!

>
>> being treated as a signed integer.
>>
>> Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation")
>> Signed-off-by: Ido Schimmel <idosch@mellanox•com>
>> Signed-off-by: Jiri Pirko <jiri@mellanox•com>
>
>[...]
>
>MBR, Sergei
>

      reply	other threads:[~2016-03-07 14:29 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-07  8:24 [patch net 0/2] mlxsw: couple of fixes Jiri Pirko
2016-03-07  8:24 ` [patch net 1/2] mlxsw: spectrum: Always decrement bridge's ref count Jiri Pirko
2016-03-07  8:24 ` [patch net 2/2] mlxsw: pci: Correctly determine if descriptor queue is full Jiri Pirko
2016-03-07 14:04   ` Sergei Shtylyov
2016-03-07 14:12     ` Ido Schimmel [this message]

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