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From: John Crispin <john@phrozen•org>
To: Andrew Lunn <andrew@lunn•ch>,
	Vivien Didelot <vivien.didelot@savoirfairelinux•com>,
	Florian Fainelli <f.fainelli@gmail•com>,
	"David S . Miller" <davem@davemloft•net>,
	Sean Wang <sean.wang@mediatek•com>
Cc: netdev@vger•kernel.org, linux-kernel@vger•kernel.org,
	John Crispin <john@phrozen•org>, Rob Herring <robh+dt@kernel•org>,
	devicetree@vger•kernel.org
Subject: [PATCH V2 1/3] Documentation: devicetree: add multiple cpu port DSA binding
Date: Tue, 30 May 2017 12:44:17 +0200	[thread overview]
Message-ID: <20170530104419.6052-1-john@phrozen.org> (raw)

Extend the DSA binding documentation, adding the new property required
when there is more than one CPU port attached to the switch.

Cc: Rob Herring <robh+dt@kernel•org>
Cc: devicetree@vger•kernel.org
Signed-off-by: John Crispin <john@phrozen•org>
---
 Documentation/devicetree/bindings/net/dsa/dsa.txt | 61 ++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt
index cfe8f64eca4f..c164eb38ccc5 100644
--- a/Documentation/devicetree/bindings/net/dsa/dsa.txt
+++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt
@@ -55,6 +55,11 @@ A user port has the following optional property:
 - label			: Describes the label associated with this port, which
                           will become the netdev name.
 
+- cpu			: Option for non "cpu"/"dsa" ports. A phandle to a
+			  "cpu" port, which will be used for passing packets
+			  from this port to the host. If not present, the first
+			  "cpu" port will be used.
+
 Port child nodes may also contain the following optional standardised
 properties, described in binding documents:
 
@@ -71,7 +76,7 @@ properties, described in binding documents:
 			  Documentation/devicetree/bindings/net/fixed-link.txt
 			  for details.
 
-Example
+Examples
 
 The following example shows three switches on three MDIO busses,
 linked into one DSA cluster.
@@ -264,6 +269,60 @@ linked into one DSA cluster.
 	};
 };
 
+The following example shows a switch that has two cpu ports each connecting
+to a different MAC.
+
+&mdio0 {
+	switch@0 {
+		compatible = "mediatek,mt7530";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			port@0 {
+				reg = <0>;
+				label = "lan0";
+				cpu = <&cpu_port1>;
+			};
+
+			port@1 {
+				reg = <1>;
+				label = "lan1";
+				cpu = <&cpu_port1>;
+			};
+
+			port@2 {
+				reg = <2>;
+				label = "lan2";
+				cpu = <&cpu_port1>;
+			};
+
+			port@3 {
+				reg = <3>;
+				label = "wan";
+				cpu = <&cpu_port2>;
+			};
+
+			cpu_port2: port@5 {
+				reg = <5>;
+				label = "cpu";
+				ethernet = <&gmac2>;
+				phy-mode = "trgmii";
+			};
+
+			cpu_port1: port@6 {
+				reg = <6>;
+				label = "cpu";
+				ethernet = <&gmac1>;
+				phy-mode = "trgmii";
+			};
+		};
+	};
+};
+
 Deprecated Binding
 ------------------
 
-- 
2.11.0

             reply	other threads:[~2017-05-30 10:44 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-30 10:44 John Crispin [this message]
2017-05-30 10:44 ` [PATCH V2 2/3] net-next: dsa: add multi cpu port support John Crispin
2017-05-30 15:38   ` kbuild test robot
2017-05-30 18:37     ` John Crispin
2017-05-30 19:15       ` Florian Fainelli
2017-05-30 19:23         ` Florian Fainelli
2017-05-30 19:45   ` Vivien Didelot
2017-05-30 19:50     ` Vivien Didelot
2017-05-30 22:56   ` Florian Fainelli
2017-05-31  0:06     ` Andrew Lunn
2017-05-31  0:16       ` Florian Fainelli
2017-05-31  0:52         ` Andrew Lunn
2017-05-30 10:44 ` [PATCH V2 3/3] net-next: dsa: mt7530: " John Crispin
2017-05-30 21:32 ` [PATCH V2 1/3] Documentation: devicetree: add multiple cpu port DSA binding Florian Fainelli
     [not found]   ` <69dd02a6-59f9-59df-f630-0ebd948451c4-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-06-07 21:10     ` Rob Herring
2017-06-07 21:35       ` Florian Fainelli
2017-06-08 19:31         ` Andrew Lunn
     [not found]           ` <20170608193112.GF20216-g2DYL2Zd6BY@public.gmane.org>
2017-06-08 19:57             ` Florian Fainelli
2017-06-07 21:42       ` Andrew Lunn

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