From: Andrew Lunn <andrew@lunn•ch>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail•com>
Cc: Florian Fainelli <f.fainelli@gmail•com>, netdev <netdev@vger•kernel.org>
Subject: Re: [Query]: DSA Understanding
Date: Mon, 13 Aug 2018 15:38:17 +0200 [thread overview]
Message-ID: <20180813133817.GA18645@lunn.ch> (raw)
In-Reply-To: <CA+V-a8tXStPqWGtJdvC0KzsgsPyGoXY7H8gGfXC+7s0dE9koaQ@mail.gmail.com>
> > I agree, this should be padding packets correctly, can you still
> > instrument cpsw to make sure that what comes to its ndo_start_xmit() is
> > ETH_ZLEN + tag_len or more?
> >
> Yes I can confirm the skb->len is always >= 62 (ETH_ZLEN + 2)
Which switch are you using?
Marvell switches use either 4 or 8 bytes of tag. Broadcom has 4, KSZ
has 1 for packets going to the switch, lan9303 has 4, mtd uses 4, qca
has 2.
Andrew
next prev parent reply other threads:[~2018-08-13 16:20 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-25 8:39 [Query]: DSA Understanding Lad, Prabhakar
2018-07-25 16:19 ` Andrew Lunn
2018-07-26 7:38 ` Lad, Prabhakar
2018-07-26 14:08 ` Andrew Lunn
2018-07-26 15:20 ` Lad, Prabhakar
2018-07-26 15:39 ` Andrew Lunn
2018-08-02 8:13 ` Lad, Prabhakar
2018-08-02 14:45 ` Andrew Lunn
2018-08-02 14:58 ` Lad, Prabhakar
2018-08-02 16:05 ` Andrew Lunn
2018-08-02 16:24 ` Florian Fainelli
2018-08-09 11:33 ` Lad, Prabhakar
2018-08-09 12:08 ` Andrew Lunn
2018-08-09 11:31 ` Lad, Prabhakar
2018-08-09 12:01 ` Andrew Lunn
2018-08-09 12:45 ` Lad, Prabhakar
2018-08-09 12:56 ` Andrew Lunn
2018-08-09 15:07 ` Lad, Prabhakar
2018-08-09 15:35 ` Andrew Lunn
2018-08-09 16:03 ` Lad, Prabhakar
2018-08-09 17:23 ` Andrew Lunn
2018-08-10 11:26 ` Lad, Prabhakar
2018-08-10 17:36 ` Florian Fainelli
2018-08-13 11:06 ` Lad, Prabhakar
2018-08-13 13:38 ` Andrew Lunn [this message]
2018-08-13 15:58 ` Lad, Prabhakar
2018-08-13 18:57 ` Florian Fainelli
2018-08-14 11:49 ` Lad, Prabhakar
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