Subject: Re: Handling an Extra Signal at PHY Reset

From: Andrew Lunn <[email-masked]>
Date: Tue, 19 Feb 2019 16:40:52 +0100

> I think the reason why we need to deal with the CONFIG pin is more
> about setting the correct I/O voltage than the PHY address (it just
> happens that the CONFIG pin configures both at once).

Hi Paul

I don't have the datasheet...

What I/O voltages are we talking about? Is the device addressable over
the MDIO bus without this configuration? Can the voltages be
configured via register writes during probe? I assume not, or you
would be doing that...

      Andrew