* [PATCH net] net: dsa: mv8e6xxx: fix number of internal PHYs for 88E6390(X)
@ 2019-03-01 18:40 Heiner Kallweit
2019-03-01 22:31 ` Andrew Lunn
0 siblings, 1 reply; 3+ messages in thread
From: Heiner Kallweit @ 2019-03-01 18:40 UTC (permalink / raw)
To: Vivien Didelot, Andrew Lunn, Florian Fainelli, David Miller
Cc: netdev@vger•kernel.org
Ports 9 and 10 don't have internal PHY's but are (dependent on the
version) SERDES/SGMII/XAUI/RXAUI ports.
Fixes: bc3931557d1d ("net: dsa: mv88e6xxx: Add number of internal PHYs")
Signed-off-by: Heiner Kallweit <hkallweit1@gmail•com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index f1f228af0..47128cae2 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -4502,7 +4502,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.name = "Marvell 88E6390",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 11,
+ .num_internal_phys = 9,
.num_gpio = 16,
.max_vid = 8191,
.port_base_addr = 0x0,
@@ -4525,7 +4525,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.name = "Marvell 88E6390X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
- .num_internal_phys = 11,
+ .num_internal_phys = 9,
.num_gpio = 16,
.max_vid = 8191,
.port_base_addr = 0x0,
--
2.21.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH net] net: dsa: mv8e6xxx: fix number of internal PHYs for 88E6390(X)
2019-03-01 18:40 [PATCH net] net: dsa: mv8e6xxx: fix number of internal PHYs for 88E6390(X) Heiner Kallweit
@ 2019-03-01 22:31 ` Andrew Lunn
2019-03-02 14:23 ` Heiner Kallweit
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Lunn @ 2019-03-01 22:31 UTC (permalink / raw)
To: Heiner Kallweit
Cc: Vivien Didelot, Florian Fainelli, David Miller,
netdev@vger•kernel.org
On Fri, Mar 01, 2019 at 07:40:59PM +0100, Heiner Kallweit wrote:
> Ports 9 and 10 don't have internal PHY's but are (dependent on the
> version) SERDES/SGMII/XAUI/RXAUI ports.
Hi Heiner
All members of the MV88E6XXX_FAMILY_6390 are 11 ports, but only 9
PHYs. So 88E6190, 88E6190X, 88E6191, and 88E6290 as well.
Andrew
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH net] net: dsa: mv8e6xxx: fix number of internal PHYs for 88E6390(X)
2019-03-01 22:31 ` Andrew Lunn
@ 2019-03-02 14:23 ` Heiner Kallweit
0 siblings, 0 replies; 3+ messages in thread
From: Heiner Kallweit @ 2019-03-02 14:23 UTC (permalink / raw)
To: Andrew Lunn
Cc: Vivien Didelot, Florian Fainelli, David Miller,
netdev@vger•kernel.org
On 01.03.2019 23:31, Andrew Lunn wrote:
> On Fri, Mar 01, 2019 at 07:40:59PM +0100, Heiner Kallweit wrote:
>> Ports 9 and 10 don't have internal PHY's but are (dependent on the
>> version) SERDES/SGMII/XAUI/RXAUI ports.
>
> Hi Heiner
>
> All members of the MV88E6XXX_FAMILY_6390 are 11 ports, but only 9
> PHYs. So 88E6190, 88E6190X, 88E6191, and 88E6290 as well.
>
Thanks for the hint, I amended the patch accordingly.
> Andrew
>
Heiner
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-03-01 18:40 [PATCH net] net: dsa: mv8e6xxx: fix number of internal PHYs for 88E6390(X) Heiner Kallweit
2019-03-01 22:31 ` Andrew Lunn
2019-03-02 14:23 ` Heiner Kallweit
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