From: Jesse Brandeburg <jesse.brandeburg@intel•com>
To: Robert Hancock <hancock@sedsystems•ca>
Cc: <netdev@vger•kernel.org>, jesse.brandeburg@intel•com
Subject: Re: [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver
Date: Mon, 3 Jun 2019 16:27:45 -0700 [thread overview]
Message-ID: <20190603162745.00007313@intel.com> (raw)
In-Reply-To: <1559603524-18288-1-git-send-email-hancock@sedsystems.ca>
On Mon, 3 Jun 2019 17:12:04 -0600
Robert Hancock <hancock@sedsystems•ca> wrote:
> This adds a driver for the PHY device implemented in the Xilinx PCS/PMA
> Core logic. This is mostly a generic gigabit PHY, except that the
> features are explicitly set because the PHY wrongly indicates it has no
> extended status register when it actually does.
>
> This version is a simplified version of the GPL 2+ version from the
> Xilinx kernel tree.
>
> Signed-off-by: Robert Hancock <hancock@sedsystems•ca>
> ---
>
> Differences from v1:
> -Removed unnecessary config_init method
> -Added comment to explain why features are explicitly set
>
> drivers/net/phy/Kconfig | 6 ++++++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/xilinx.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 58 insertions(+)
> create mode 100644 drivers/net/phy/xilinx.c
>
Seems fine.
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel•com>
next prev parent reply other threads:[~2019-06-03 23:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-03 23:12 [PATCH net-next v2] net: phy: xilinx: add Xilinx PHY driver Robert Hancock
2019-06-03 23:27 ` Jesse Brandeburg [this message]
2019-06-04 2:39 ` Florian Fainelli
2019-06-04 5:37 ` Heiner Kallweit
2019-06-04 16:39 ` Robert Hancock
2019-06-04 16:54 ` Andrew Lunn
2019-06-04 17:37 ` Robert Hancock
2019-06-04 17:54 ` Heiner Kallweit
2019-06-04 18:12 ` Andrew Lunn
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