Subject: Re: [PATCH net-next 05/18] net: axienet: Allow explicitly setting MDIO clock divisor

From: Andrew Lunn <[email-masked]>
Date: Tue, 4 Jun 2019 04:33:01 +0200

On Mon, Jun 03, 2019 at 03:57:04PM -0600, Robert Hancock wrote:
> This driver was previously always calculating the MDIO clock divisor
> (from AXI bus clock to MDIO bus clock) based on the CPU clock frequency,
> but that simplistic method only works on the MicroBlaze platform. This
> really has to be a platform configuration setting as there is no way the
> kernel can know the clock speed of the AXI bus in the general case.
> 
> Add an optional xlnx,mdio-clock-divisor device tree property that can be
> used to explicitly set the MDIO bus divisor. This must be set based on the
> AXI bus clock rate being used in the FPGA logic so that the resulting
> MDIO clock rate is no greater than 2.5 MHz.

Rather than the clock divisor, the binding should reference the clock,
using the standard DT clock properties. You can then
clk_prepare_enable() the clock to ensure nobody turns it off. You can
get its rate in order to calculate the divisor. And it lays the
foundation for power saving in that you can turn the clock off between
MDIO transactions, using the runtime PM APIS.

     Andrew