Subject: Re: [PATCH net-next 07/18] net: axienet: Re-initialize MDIO registers properly after reset

From: Andrew Lunn <[email-masked]>
Date: Tue, 4 Jun 2019 04:43:55 +0200

On Mon, Jun 03, 2019 at 03:57:06PM -0600, Robert Hancock wrote:
> The MDIO clock divisor register setting was only applied on the initial
> startup when the driver was loaded. However, this setting is cleared
> when the device is reset, such as would occur when the interface was
> taken down and brought up again, and so the MDIO bus would be
> non-functional afterwards.
> 
> Split up the MDIO bus setup and enable into separate functions and
> re-enable the bus after a device reset, to ensure that the MDIO
> registers are set properly. This also allows us to remove direct access
> to MDIO registers in xilinx_axienet_main.c and centralize them all in
> xilinx_axienet_mdio.c.

Hi Robert

MDIO is a shared bus. There can be multiple PHYs on it, an ethernet
switch, etc. So you need to be careful here. Before you hit the reset,
you need to lock the MDIO bus, bus->mdio_lock, do the reset, and then
unlock the bus.

Also, as soon as you register the bus, it needs to be usable. Your
axienet_mdio_setup() needs to set the divisor before it registers the
bus.

	Andrew