Subject: Re: [PATCH net-next 2/2] dpaa_eth: support all modes with rate adapting PHYs

From: Russell King - ARM Linux admin <[email-masked]>
Date: Wed, 29 Jan 2020 13:34:57 +0000

On Thu, Jan 23, 2020 at 07:20:58AM +0000, Madalin Bucur (OSS) wrote:
> There has been a long email thread [1] related to this particular issue.
> Please note USXGMII is one of the supported modes of the AQR PHYs but
> unfortunately not a mode our SoC is capable to use. The DPAA 1 platforms
> do not support USXGMII, they use a serial interface to the PHY, called
> anywhere in the DPAA SoC and PHY datasheets XFI. We're left with "xgmii"
> compatible in the device tree because that's what was available at the
> time in the kernel for 10G and because in the SoC XGMII is the actual
> MII that connects the MAC to the SoC internal blocks that are part of
> the physical layer. Because we have an internal PCS, the DPAA SoC to
> external PHY connection is a PHY-layer internal connection, that has
> no official denomination derived from a standard. In the industry, this
> is called XFI.

People in industry call 1000BASE-X "SGMII" as well, despite SGMII being
a Cisco modification of 1000BASE-X.  They are compatible up to a point
but they do not inter-operate.  What terms industry uses does not make
those terms correct, and does not mean we should continue their cockups.
The same is true for the XFI.  Get over it.

-- 
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