Subject: Re: [PATCH net] net: phy: marvell10g: limit soft reset to 88x3310

From: Russell King - ARM Linux admin <[email-masked]>
Date: Tue, 21 Apr 2020 10:17:20 +0100

On Tue, Apr 21, 2020 at 12:04:46PM +0300, Baruch Siach wrote:
> The MV_V2_PORT_CTRL_SWRST bit in MV_V2_PORT_CTRL is reserved on 88E2110.
> Setting SWRST on 88E2110 breaks packets transfer after interface down/up
> cycle.
> 
> Fixes: 8f48c2ac85ed ("net: marvell10g: soft-reset the PHY when coming out of low power")
> Signed-off-by: Baruch Siach <[email-masked]>

Okay, the presence of 88E2110 combined with 88X3310 support is going to
be a constant source of pain in terms of maintanence, since I know
nothing about this PHY, nor do I have any way to test my changes there.

I think we need to think about how to deal with that - do we split the
code, so that 88X3310 can be maintained separately from 88E2110 (even
though most of the code may be the same), or can someone send me a board
that has the 88E2110 on (I can't purchase as I have no funds to do so.)

So, I guess splitting the code is likely to be the only solution.

> ---
>  drivers/net/phy/marvell10g.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
> index d3cb88651ad2..601686f64341 100644
> --- a/drivers/net/phy/marvell10g.c
> +++ b/drivers/net/phy/marvell10g.c
> @@ -263,7 +263,8 @@ static int mv3310_power_up(struct phy_device *phydev)
>  	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
>  				 MV_V2_PORT_CTRL_PWRDOWN);
>  
> -	if (priv->firmware_ver < 0x00030000)
> +	if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
> +	    priv->firmware_ver < 0x00030000)
>  		return ret;
>  
>  	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
> -- 
> 2.26.1
> 
> 

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