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From: Andrew Lunn <andrew@lunn•ch>
To: Andy Duan <fugang.duan@nxp•com>
Cc: Leonard Crestez <leonard.crestez@nxp•com>,
	David Miller <davem@davemloft•net>,
	netdev <netdev@vger•kernel.org>,
	Chris Healy <Chris.Healy@zii•aero>,
	dl-linux-imx <linux-imx@nxp•com>, Chris Healy <cphealy@gmail•com>
Subject: Re: [EXT] Re: [PATCH] net: ethernet: fec: Replace interrupt driven MDIO with polled IO
Date: Tue, 28 Apr 2020 15:34:45 +0200	[thread overview]
Message-ID: <20200428133445.GA21352@lunn.ch> (raw)
In-Reply-To: <HE1PR0402MB2745B6388B6BF7306629A305FFAC0@HE1PR0402MB2745.eurprd04.prod.outlook.com>

> Andrew, after investigate the issue, there have one MII event coming later then
> clearing MII pending event when writing MSCR register (MII_SPEED).
> 
> Check the rtl design by co-working with our IC designer, the MII event generation
> condition:
> - writing MSCR:
> 	- mmfr[31:0]_not_zero & mscr[7:0]_is_zero & mscr_reg_data_in[7:0] != 0
> - writing MMFR:
> 	- mscr[7:0]_not_zero
> 	
> mmfr[31:0]: current MMFR register value
> mscr[7:0]: current MSCR register value
> mscr_reg_data_in[7:0]: the value wrote to MSCR
> 
> 
> Below patch can fix the block issue:
> --- a/drivers/net/ethernet/freescale/fec_main.c
> +++ b/drivers/net/ethernet/freescale/fec_main.c
> @@ -2142,6 +2142,15 @@ static int fec_enet_mii_init(struct platform_device *pdev)
>         if (suppress_preamble)
>                 fep->phy_speed |= BIT(7);
> 
> +       /*
> +        * Clear MMFR to avoid to generate MII event by writing MSCR.
> +        * MII event generation condition:
> +        * - writing MSCR:
> +        *      - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & mscr_reg_data_in[7:0] != 0
> +        * - writing MMFR:
> +        *      - mscr[7:0]_not_zero
> +        */
> +       writel(0, fep->hwp + FEC_MII_DATA);
>         writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

Hi Andy

Thanks for digging into the internal of the FEC. Just to make sure i
understand this correctly:

In fec_enet_mii_init() we have:

        holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;

        fep->phy_speed = mii_speed << 1 | holdtime << 8;

        writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);

        /* Clear any pending transaction complete indication */
        writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);

You are saying this write to the FEC_MII_SPEED register can on some
SoCs trigger an FEC_ENET_MII event. And because it does not happen
immediately, it happens after the clear which is performed here?
Sometime later we then go into fec_enet_mdio_wait(), the event is
still pending, so we read the FEC_MII_DATA register too early?

But this does not fully explain the problem. This should only affect
the first MDIO transaction, because as we exit fec_enet_mdio_wait()
the event is cleared. But Leonard reported that all reads return 0,
not just the first.

    Andrew


  reply	other threads:[~2020-04-28 13:34 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-14  0:45 [PATCH] net: ethernet: fec: Replace interrupt driven MDIO with polled IO Andrew Lunn
2020-04-14  3:07 ` [EXT] " Andy Duan
2020-04-14  3:49   ` Andrew Lunn
2020-04-14  5:12     ` Andy Duan
2020-04-14 12:55       ` Andrew Lunn
2020-04-14 23:38 ` David Miller
2020-04-15  0:20   ` Andrew Lunn
2020-04-27 15:19 ` Leonard Crestez
2020-04-27 15:29   ` Andy Duan
2020-04-27 15:37   ` Andrew Lunn
2020-04-27 16:37   ` Andrew Lunn
2020-04-27 16:48     ` Fabio Estevam
2020-04-27 16:46   ` Andrew Lunn
2020-04-27 17:48     ` [EXT] " Andy Duan
2020-04-27 20:00     ` Leonard Crestez
2020-04-27 20:13       ` Andrew Lunn
2020-04-28  7:50         ` [EXT] " Andy Duan
2020-04-28 13:34           ` Andrew Lunn [this message]
2020-04-28 13:50             ` Andy Duan
2020-04-28 14:29               ` Andrew Lunn
  -- strict thread matches above, loose matches on Subject: below --
2020-10-20  2:14 Greg Ungerer
2020-10-20  2:40 ` Andrew Lunn
2020-10-20  3:02   ` [EXT] " Andy Duan
2020-10-20 13:06     ` Chris Healy
2020-10-20 13:52       ` Andy Duan
2020-10-20 13:08     ` Andrew Lunn
2020-10-21  1:51   ` Greg Ungerer
2020-10-21  2:19     ` [EXT] " Andy Duan
2020-10-21  2:37       ` Greg Ungerer
2020-10-21 13:37     ` Andrew Lunn
2020-10-22  1:14       ` Greg Ungerer
2020-10-22  2:39         ` [EXT] " Andy Duan
2020-10-22  9:04         ` Andy Duan
2020-10-27  0:17           ` Greg Ungerer
2020-10-27  1:33             ` Andy Duan

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