Subject: Re: [PATCH net v2 0/4] net: ethernet: fec: move GPR reigster offset and bit into DT

From: Andrew Lunn <[email-masked]>
Date: Mon, 25 May 2020 15:54:33 +0200

On Mon, May 25, 2020 at 03:09:25PM +0800, [email-masked] wrote:
> From: Fugang Duan <[email-masked]>
> 
> The commit da722186f654 (net: fec: set GPR bit on suspend by DT configuration) set the GPR reigster offset and bit in driver for wol feature.

The cover letter gets committed as the merge commit message. So please
wrap long longs.

> It bring trouble to enable wol feature on imx6sx/imx6ul/imx7d
> platforms that have multiple ethernet instances with different GPR
> bit for stop mode control. So the patch set is to move GPR reigster

register

> offset and bit define into DT, and enable
> imx6q/imx6dl/imx6sx/imx6ul/imx7d stop mode support.

> 
> Currently, below NXP i.MX boards support wol:
> - imx6q/imx6dl sabresd
> - imx6sx sabreauto
> - imx7d sdb
> 
> imx6q/imx6dl sarebsd board dts file miss the property "fsl,magic-packet;", so patch#4 is to add the property for stop mode support.

sabresd?

	Andrew