Subject: Re: [PATCH 2/2] net: phy: Associate device node with fixed PHY

From: Russell King - ARM Linux admin <[email-masked]>
Date: Mon, 3 Aug 2020 10:07:16 +0100

On Mon, Aug 03, 2020 at 08:33:19AM +0000, Madalin Bucur (OSS) wrote:
> > -----Original Message-----
> > From: [email-masked] <[email-masked]> On
> > Behalf Of Andrew Lunn
> > Sent: 01 August 2020 18:11
> > To: Russell King - ARM Linux admin <[email-masked]>
> > Cc: Vikas Singh <[email-masked]>; [email-masked];
> > [email-masked]; [email-masked]; Calvin Johnson (OSS)
> > <[email-masked]>; kuldip dwivedi
> > <[email-masked]>; Madalin Bucur (OSS)
> > <[email-masked]>; Vikas Singh <[email-masked]>
> > Subject: Re: [PATCH 2/2] net: phy: Associate device node with fixed PHY
> > 
> > On Sat, Aug 01, 2020 at 10:41:32AM +0100, Russell King - ARM Linux admin
> > wrote:
> > > On Sat, Aug 01, 2020 at 09:52:52AM +0530, Vikas Singh wrote:
> > > > Hi Andrew,
> > > >
> > > > Please refer to the "fman" node under
> > > > linux/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
> > > > I have two 10G ethernet interfaces out of which one is of fixed-link.
> > >
> > > Please do not top post.
> > >
> > > How does XGMII (which is a 10G only interface) work at 1G speed?  Is
> > > what is in DT itself a hack because fixed-phy doesn't support 10G
> > > modes?
> > 
> > My gut feeling is there is some hack going on here, which is why i'm
> > being persistent at trying to understand what is actually going on
> > here.
> 
> Hi Andrew,
> 
> That platform used 1G fixed link there since there was no support for
> 10G fixed link at the time. PHYlib could have tolerated 10G speed there
> With a one-liner.

That statement is false.  It is not a "one liner".  fixed-phy exposes
the settings to userspace as a Clause 22 PHY register set, and the
Clause 22 register set does not support 10G.  So, a "one liner" would
just be yet another hack.  Adding Clause 45 PHY emulation support
would be a huge task.

> I understand that PHYLink is working to describe this
> Better, but it was not there at that time. Adding the dependency on
> PHYLink was not desirable as most of the users for the DPAA 1 platforms
> were targeting kernels before the PHYLink introduction (and last I've
> looked, it's still under development, with unstable APIs so we'll
> take a look at this later, when it settles).

I think you need to read Documentation/process/stable-api-nonsense.rst
particularly the section "Stable Kernel Source Interfaces".

phylink is going to be under development for quite some time to come
as requirements evolve.  For example, when support for QSFP interfaces
is eventually worked out, I suspect there will need to be some further
changes to the driver interface.  This is completely normal.

Now, as to the stability of the phylink API to drivers, it has in fact
been very stable - it has only changed over the course of this year to
support split PCS, a necessary step for DPAA2 and a few others.  It has
been around in mainline for two years, and has been around much longer
than that, and during that time it has been in mainline, the MAC facing
interface has not changed until recently.

So, I find your claim to be quite unreasonable.

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