Subject: Re: [PATCH v2 0/7] remove different PHY fixups

From: Russell King - ARM Linux admin <[email-masked]>
Date: Tue, 13 Apr 2021 11:51:44 +0100

On Tue, Apr 13, 2021 at 12:00:45PM +0200, Lucas Stach wrote:
> I agree with the opinion that those PHY fixups introduce more harm than
> good. Essentially they are pushing board specific configuration values
> into the PHY, without any checks that the fixup is even running on the
> specific board it was targeted at.

Yes and no. The problem is, that's an easy statement to make when one
doesn't understand what they're all doing.

Some are "board specific" in that the normal setup for e.g. iMX6 would
be to enable clock output from the AR8035 PHY and feed that into the
iMX6 - as far as I'm aware, that's the only working configuration for
that SoC and PHY. However, it's also true that this fixup should not
be applied unconditionally.

Then there's SmartEEE - it has been found that the PHY defaults for
this lead to link drops independent of the board and SoC that it is
connected to. It seems that the PHY is essentially broken - it powers
up with SmartEEE enabled, and when connected to another SmartEEE
supporting device, it seems guaranteed that it will result in link
drops in its default configuration.

Freescale's approach has apparently been to unconditionally disable
SmartEEE for all their platforms because of this. With a bit of
research however (as has been done by Jon and myself) we've found
that increasing the Tw parameter for 1G connections results in a
much more stable link.

So, just saying that these are bad without actually understanding what
they are doing is _also_ bad.

-- 
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