From: Saeed Mahameed <saeed@kernel•org>
To: "David S. Miller" <davem@davemloft•net>,
Jakub Kicinski <kuba@kernel•org>
Cc: netdev@vger•kernel.org, Tariq Toukan <tariqt@nvidia•com>,
Yevgeny Kliteynik <kliteyn@nvidia•com>,
Alex Vesker <valex@nvidia•com>,
Saeed Mahameed <saeedm@nvidia•com>
Subject: [net 8/8] net/mlx5: DR, Create multi-destination flow table with level less than 64
Date: Tue, 1 Jun 2021 18:37:23 -0700 [thread overview]
Message-ID: <20210602013723.1142650-9-saeed@kernel.org> (raw)
In-Reply-To: <20210602013723.1142650-1-saeed@kernel.org>
From: Yevgeny Kliteynik <kliteyn@nvidia•com>
Flow table that contains flow pointing to multiple flow tables or multiple
TIRs must have a level lower than 64. In our case it applies to muli-
destination flow table.
Fix the level of the created table to comply with HW Spec definitions, and
still make sure that its level lower than SW-owned tables, so that it
would be possible to point from the multi-destination FW table to SW
tables.
Fixes: 34583beea4b7 ("net/mlx5: DR, Create multi-destination table for SW-steering use")
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia•com>
Reviewed-by: Alex Vesker <valex@nvidia•com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia•com>
---
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c | 3 ++-
include/linux/mlx5/mlx5_ifc.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
index 1fbcd012bb85..7ccfd40586ce 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_fw.c
@@ -112,7 +112,8 @@ int mlx5dr_fw_create_md_tbl(struct mlx5dr_domain *dmn,
int ret;
ft_attr.table_type = MLX5_FLOW_TABLE_TYPE_FDB;
- ft_attr.level = dmn->info.caps.max_ft_level - 2;
+ ft_attr.level = min_t(int, dmn->info.caps.max_ft_level - 2,
+ MLX5_FT_MAX_MULTIPATH_LEVEL);
ft_attr.reformat_en = reformat_req;
ft_attr.decap_en = reformat_req;
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 6d16eed6850e..eb86e80e4643 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1289,6 +1289,8 @@ enum mlx5_fc_bulk_alloc_bitmask {
#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
+#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
+
enum {
MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
--
2.31.1
prev parent reply other threads:[~2021-06-02 1:37 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-02 1:37 [pull request][net 0/8] mlx5 fixes 2021-06-01 Saeed Mahameed
2021-06-02 1:37 ` [net 1/8] net/mlx5e: Fix incompatible casting Saeed Mahameed
2021-06-02 17:10 ` Jakub Kicinski
2021-06-02 20:30 ` patchwork-bot+netdevbpf
2021-06-03 21:02 ` David Laight
2021-06-02 1:37 ` [net 2/8] net/mlx5e: Disable TLS offload for uplink representor Saeed Mahameed
2021-06-02 1:37 ` [net 3/8] net/mlx5: Check firmware sync reset requested is set before trying to abort it Saeed Mahameed
2021-06-02 1:37 ` [net 4/8] net/mlx5e: Check for needed capability for cvlan matching Saeed Mahameed
2021-06-02 1:37 ` [net 5/8] net/mlx5e: Fix adding encap rules to slow path Saeed Mahameed
2021-06-02 1:37 ` [net 6/8] net/mlx5e: Fix HW TS with CQE compression according to profile Saeed Mahameed
2021-06-02 1:37 ` [net 7/8] net/mlx5e: Fix conflict with HW TS and CQE compression Saeed Mahameed
2021-06-02 1:37 ` Saeed Mahameed [this message]
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