Subject: Re: [PATCH net-next V2] net: phy: marvell10g: enable WoL for mv2110

From: "Russell King (Oracle)" <[email-masked]>
Date: Tue, 29 Jun 2021 14:03:10 +0100

On Tue, Jun 29, 2021 at 06:55:54PM +0800, Ling Pei Lee wrote:
> From: Voon Weifeng <[email-masked]>
> 
> Basically it is just to enable to WoL interrupt and enable WoL detection.
> Then, configure the MAC address into address detection register.
> 
> Change Log:
>  V2:
>  (1) Reviewer Marek request to rorganize code to readable way.
>  (2) Reviewer Rusell request to put phy_clear_bits_mmd() outside of if(){}else{}
>      and modify return ret to return phy_clear_bits_mmd().
>  (3) Reviewer Rusell request to add return on phy_read_mmd() in set_wol().
>  (4) Reorganize register layout to be put before MV_V2_TEMP_CTRL.

I actually said:

"Please put these new register definitions in address order. This list
is first sorted by MMD and then by address. So these should be before
the definition of MV_V2_TEMP_CTRL."

Which you have partially done.

> @@ -99,6 +100,17 @@ enum {
>  	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN	= 0x5,
>  	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
>  	MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII			= 0x7,
> +	MV_V2_MAGIC_PKT_WORD0	= 0xf06b,
> +	MV_V2_MAGIC_PKT_WORD1	= 0xf06c,
> +	MV_V2_MAGIC_PKT_WORD2	= 0xf06d,
> +	/* Wake on LAN registers */
> +	MV_V2_WOL_CTRL		= 0xf06e,
> +	MV_V2_WOL_STS		= 0xf06f,
> +	MV_V2_WOL_CLEAR_STS	= BIT(15),
> +	MV_V2_WOL_MAGIC_PKT_EN	= BIT(0),
> +	MV_V2_PORT_INTR_STS	= 0xf040,
> +	MV_V2_PORT_INTR_MASK	= 0xf043,
> +	MV_V2_WOL_INTR_EN	= BIT(8),

Clearly MV_V2_PORT_INTR_STS is at a lower address than
MV_V2_MAGIC_PKT_WORD0, so the list is not sorted as it originally was.

Apart from that, the rest of the patch looks good, thanks!

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