Subject: Re: [PATCH v2 net-next 8/9] net: mscc: ocelot: set up tag_8021q CPU ports independent of user port affinity

From: Jakub Kicinski <[email-masked]>
Date: Thu, 18 Aug 2022 20:58:56 -0700

On Thu, 18 Aug 2022 16:52:55 +0300 Vladimir Oltean wrote:
> This is a partial revert of commit c295f9831f1d ("net: mscc: ocelot:
> switch from {,un}set to {,un}assign for tag_8021q CPU ports"), because
> as it turns out, this isn't how tag_8021q CPU ports under a LAG are
> supposed to work.
> 
> Under that scenario, all user ports are "assigned" to the single
> tag_8021q CPU port represented by the logical port corresponding to the
> bonding interface. So one CPU port in a LAG would have is_dsa_8021q_cpu
> set to true (the one whose physical port ID is equal to the logical port
> ID), and the other one to false.
> 
> In turn, this makes 2 undesirable things happen:
> 
> (1) PGID_CPU contains only the first physical CPU port, rather than both
> (2) only the first CPU port will be added to the private VLANs used by
>     ocelot for VLAN-unaware bridging
> 
> To make the driver behave in the same way for both bonded CPU ports, we
> need to bring back the old concept of setting up a port as a tag_8021q
> CPU port, and this is what deals with VLAN membership and PGID_CPU
> updating. But we also need the CPU port "assignment" (the user to CPU
> port affinity), and this is what updates the PGID_SRC forwarding rules.
> 
> All DSA CPU ports are statically configured for tag_8021q mode when the
> tagging protocol is changed to ocelot-8021q. User ports are "assigned"
> to one CPU port or the other dynamically (this will be handled by a
> future change).

ERROR: modpost: "ocelot_port_teardown_dsa_8021q_cpu" [drivers/net/dsa/ocelot/mscc_felix.ko] undefined!
ERROR: modpost: "ocelot_port_teardown_dsa_8021q_cpu" [drivers/net/dsa/ocelot/mscc_seville.ko] undefined!