From: Saeed Mahameed <saeed@kernel•org>
To: Saeed Mahameed <saeedm@nvidia•com>, Leon Romanovsky <leonro@nvidia•com>
Cc: "David S. Miller" <davem@davemloft•net>,
Jakub Kicinski <kuba@kernel•org>, Paolo Abeni <pabeni@redhat•com>,
Eric Dumazet <edumazet@google•com>,
netdev@vger•kernel.org, Tariq Toukan <tariqt@nvidia•com>,
Jason Gunthorpe <jgg@nvidia•com>,
linux-rdma@vger•kernel.org, "Liu,
Changcheng" <jerrliu@nvidia•com>,
Liu@vger•kernel.org, Mark Bloch <mbloch@nvidia•com>
Subject: [PATCH mlx5-next 06/14] net/mlx5: Lag, enable hash mode by default for all NICs
Date: Wed, 7 Sep 2022 16:36:28 -0700 [thread overview]
Message-ID: <20220907233636.388475-7-saeed@kernel.org> (raw)
In-Reply-To: <20220907233636.388475-1-saeed@kernel.org>
From: "Liu, Changcheng" <jerrliu@nvidia•com>
The firmware supports adding a steering rule to catch egress traffic
of the QPs/TISs which are set port affinity explicitly in hash mode.
Enable that mode for NICS with 2 ports as well.
Signed-off-by: Liu, Changcheng <jerrliu@nvidia•com>
Reviewed-by: Mark Bloch <mbloch@nvidia•com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia•com>
---
.../net/ethernet/mellanox/mlx5/core/lag/lag.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
index d4d4d1d1e8c7..97c4a525226b 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c
@@ -484,21 +484,22 @@ void mlx5_modify_lag(struct mlx5_lag *ldev,
mlx5_lag_drop_rule_setup(ldev, tracker);
}
-#define MLX5_LAG_ROCE_HASH_PORTS_SUPPORTED 4
static int mlx5_lag_set_port_sel_mode_roce(struct mlx5_lag *ldev,
unsigned long *flags)
{
- struct lag_func *dev0 = &ldev->pf[MLX5_LAG_P1];
+ struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
- if (ldev->ports == MLX5_LAG_ROCE_HASH_PORTS_SUPPORTED) {
- /* Four ports are support only in hash mode */
- if (!MLX5_CAP_PORT_SELECTION(dev0->dev, port_select_flow_table))
- return -EINVAL;
- set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags);
+ if (!MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table)) {
if (ldev->ports > 2)
- ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS;
+ return -EINVAL;
+ return 0;
}
+ if (ldev->ports > 2)
+ ldev->buckets = MLX5_LAG_MAX_HASH_BUCKETS;
+
+ set_bit(MLX5_LAG_MODE_FLAG_HASH_BASED, flags);
+
return 0;
}
--
2.37.2
next prev parent reply other threads:[~2022-09-07 23:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-07 23:36 [PATCH mlx5-next 00/14] mlx5-next updates 2022-09-07 Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 01/14] net/mlx5: Expose NPPS related registers Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 02/14] net/mlx5: Add support for NPPS with real time mode Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 03/14] net/mlx5: add IFC bits for bypassing port select flow table Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 04/14] RDMA/mlx5: Don't set tx affinity when lag is in hash mode Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 05/14] net/mlx5: Lag, set active ports if support bypass port select flow table Saeed Mahameed
2022-09-07 23:36 ` Saeed Mahameed [this message]
2022-09-07 23:36 ` [PATCH mlx5-next 07/14] net/mlx5: detect and enable " Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 08/14] net/mlx5: Remove unused functions Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 09/14] net/mlx5: Remove unused structs Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 10/14] net/mlx5: Remove from FPGA IFC file not-needed definitions Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 11/14] net/mlx5e: Rename from tls to transport static params Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 12/14] net/mlx5: Add NVMEoTCP caps, HW bits, 128B CQE and enumerations Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 13/14] net/mlx5: Add IFC bits for general obj create param Saeed Mahameed
2022-09-07 23:36 ` [PATCH mlx5-next 14/14] net/mlx5: Add IFC bits and enums for crypto key Saeed Mahameed
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