Subject: Re: [PATCH v2 net-next 09/11] net: ethernet: mtk_eth_wed: add wed support for mt7986 chipset

From: kernel test robot <[email-masked]>
Date: Wed, 14 Sep 2022 04:17:47 +0800

Hi Lorenzo,

I love your patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    https://github.com/intel-lab-lkp/linux/commits/Lorenzo-Bianconi/Add-WED-support-for-MT7986-chipset/20220914-020432
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git c9ae520ac3faf2f272b5705b085b3778c7997ec8
config: loongarch-allyesconfig
compiler: loongarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/intel-lab-lkp/linux/commit/a92faa2f93f3bee94adae20cf99bf600a3126bad
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review Lorenzo-Bianconi/Add-WED-support-for-MT7986-chipset/20220914-020432
        git checkout a92faa2f93f3bee94adae20cf99bf600a3126bad
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=loongarch SHELL=/bin/bash drivers/net/ethernet/mediatek/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email-masked]>

All warnings (new ones prefixed by >>):

   drivers/net/ethernet/mediatek/mtk_wed.c: In function 'mtk_wed_bus_init':
>> drivers/net/ethernet/mediatek/mtk_wed.c:361:13: warning: variable 'val' set but not used [-Wunused-but-set-variable]
     361 |         u32 val;
         |             ^~~

vim +/val +361 drivers/net/ethernet/mediatek/mtk_wed.c

   354	
   355	#define PCIE_BASE_ADDR0		0x11280000
   356	static void
   357	mtk_wed_bus_init(struct mtk_wed_device *dev)
   358	{
   359		struct device_node *np = dev->hw->eth->dev->of_node;
   360		struct regmap *regs;
 > 361		u32 val;
   362	
   363		regs = syscon_regmap_lookup_by_phandle(np, "mediatek,wed-pcie");
   364		if (IS_ERR(regs))
   365			return;
   366	
   367		regmap_update_bits(regs, 0, BIT(0), BIT(0));
   368	
   369		wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
   370			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
   371	
   372		/* pcie interrupt control: pola/source selection */
   373		wed_set(dev, MTK_WED_PCIE_INT_CTRL,
   374			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
   375			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
   376		wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
   377	
   378		val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
   379		val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
   380		wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
   381		wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
   382	
   383		val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
   384		val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
   385	
   386		/* pcie interrupt status trigger register */
   387		wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
   388		wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
   389	
   390		/* pola setting */
   391		val = wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
   392		wed_set(dev, MTK_WED_PCIE_INT_CTRL, MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
   393	}
   394	

-- 
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https://01.org/lkp