Subject: [PATCH net 2/3] amd-xgbe: enable PLL_CTL for fixed PHY modes only

From: Raju Rangoju <[email-masked]>
Date: Thu, 6 Oct 2022 19:24:39 +0530

PLL control setting(HW RRCM) is needed only in fixed PHY configuration
to fix the peer-peer issues. Without the PLL control setting, the link
up takes longer time in a fixed phy configuration.

Driver implements SW RRCM for Autoneg On configuration, hence PLL
control setting (HW RRCM) is not needed for AN On configuration, and
can be skipped.

Also, PLL re-initialization is not needed for PHY Power Off and RRCM
commands. Otherwise, they lead to mailbox errors. Added the changes
accordingly.

Fixes: daf182d360e5 ("net: amd-xgbe: Toggle PLL settings during rate change")
Signed-off-by: Raju Rangoju <[email-masked]>
---
 drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 21 +++++++++++++--------
 drivers/net/ethernet/amd/xgbe/xgbe.h        | 10 ++++++++++
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
index 19b943eba560..23fbd89a29df 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c
@@ -1979,13 +1979,16 @@ static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
 
 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
 {
-	XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
-			 XGBE_PMA_PLL_CTRL_MASK,
-			 enable ? XGBE_PMA_PLL_CTRL_ENABLE
-				: XGBE_PMA_PLL_CTRL_DISABLE);
+	/* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
+	if (pdata->phy.autoneg == AUTONEG_DISABLE) {
+		XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+				 XGBE_PMA_PLL_CTRL_MASK,
+				 enable ? XGBE_PMA_PLL_CTRL_ENABLE
+					: XGBE_PMA_PLL_CTRL_DISABLE);
 
-	/* Wait for command to complete */
-	usleep_range(100, 200);
+		/* Wait for command to complete */
+		usleep_range(100, 200);
+	}
 }
 
 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
@@ -2029,8 +2032,10 @@ static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
 	xgbe_phy_rx_reset(pdata);
 
 reenable_pll:
-	/* Enable PLL re-initialization */
-	xgbe_phy_pll_ctrl(pdata, true);
+	/* Enable PLL re-initialization, not needed for PHY Power Off cmd */
+	if (cmd != XGBE_MAILBOX_CMD_POWER_OFF &&
+	    cmd != XGBE_MAILBOX_CMD_RRCM)
+		xgbe_phy_pll_ctrl(pdata, true);
 }
 
 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index 49d23abce73d..c7865681790c 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -611,6 +611,16 @@ enum xgbe_mdio_mode {
 	XGBE_MDIO_MODE_CL45,
 };
 
+enum XGBE_MAILBOX_CMD {
+	XGBE_MAILBOX_CMD_POWER_OFF	= 0,
+	XGBE_MAILBOX_CMD_SET_1G		= 1,
+	XGBE_MAILBOX_CMD_SET_2_5G	= 2,
+	XGBE_MAILBOX_CMD_SET_10G_SFI	= 3,
+	XGBE_MAILBOX_CMD_SET_10G_KR	= 4,
+	XGBE_MAILBOX_CMD_RRCM		= 5,
+	XGBE_MAILBOX_CMD_UNKNOWN	= 6
+};
+
 struct xgbe_phy {
 	struct ethtool_link_ksettings lks;
 
-- 
2.25.1