From: Saeed Mahameed <saeed@kernel•org>
To: "David S. Miller" <davem@davemloft•net>,
Jakub Kicinski <kuba@kernel•org>, Paolo Abeni <pabeni@redhat•com>,
Eric Dumazet <edumazet@google•com>
Cc: Saeed Mahameed <saeedm@nvidia•com>,
netdev@vger•kernel.org, Tariq Toukan <tariqt@nvidia•com>,
Gal Pressman <gal@nvidia•com>
Subject: [net-next 04/15] net/mlx5e: Add padding when needed in UMR WQEs
Date: Tue, 29 Nov 2022 21:11:41 -0800 [thread overview]
Message-ID: <20221130051152.479480-5-saeed@kernel.org> (raw)
In-Reply-To: <20221130051152.479480-1-saeed@kernel.org>
From: Tariq Toukan <tariqt@nvidia•com>
Per the device spec, MTTs/KLMs list in a UMR WQE must be aligned to 64B.
Per our SW design, the MTT/KLMs list would need alignment only if it's
too small, for example on PPC when PAGE_SIZE is 64KB, and only 4 pages
are needed to cover a MPWQE of size 256KB.
Padding, if needed, is taken into account when calculating the UMR WQE
fields (ds_cnt and xlt_octowords), however no entries are provided,
instead garbage is passed.
No real harm though, as these parts act as gaps between the RX MPWQEs
and not used by any of them. Hence, in practice, device does not try to
write any incoming packet to them. Still, prefer providing clean padding
marking the end of the list, and do not map garbage into the RQ memory
region.
Signed-off-by: Tariq Toukan <tariqt@nvidia•com>
Reviewed-by: Gal Pressman <gal@nvidia•com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia•com>
---
drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 11 +++++++++++
include/linux/mlx5/device.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index b1ea0b995d9c..8d71736116e0 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -727,6 +727,17 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
};
}
+ /* Pad if needed, in case the value set to ucseg->xlt_octowords
+ * in mlx5e_build_umr_wqe() needed alignment.
+ */
+ if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) {
+ int pad = ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT) -
+ rq->mpwqe.pages_per_wqe;
+
+ memset(&umr_wqe->inline_mtts[rq->mpwqe.pages_per_wqe], 0,
+ sizeof(*umr_wqe->inline_mtts) * pad);
+ }
+
bitmap_zero(wi->xdp_xmit_bitmap, rq->mpwqe.pages_per_wqe);
wi->consumed_strides = 0;
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index eb3fac30488b..97275965f156 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -294,6 +294,7 @@ enum {
#define MLX5_UMR_MTT_ALIGNMENT 0x40
#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
+#define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_MTT_ALIGNMENT / sizeof(struct mlx5_mtt))
#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
--
2.38.1
next prev parent reply other threads:[~2022-11-30 5:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-30 5:11 [pull request][net-next 00/15] mlx5 updates 2022-11-29 Saeed Mahameed
2022-11-30 5:11 ` [net-next 01/15] net/mlx5e: Remove unneeded io-mapping.h #include Saeed Mahameed
2022-12-01 6:40 ` patchwork-bot+netdevbpf
2022-11-30 5:11 ` [net-next 02/15] net/mlx5e: Replace zero-length arrays with DECLARE_FLEX_ARRAY() helper Saeed Mahameed
2022-11-30 5:11 ` [net-next 03/15] net/mlx5: Remove unused ctx variables Saeed Mahameed
2022-11-30 5:11 ` Saeed Mahameed [this message]
2022-11-30 5:11 ` [net-next 05/15] net/mlx5: Remove unused UMR MTT definitions Saeed Mahameed
2022-11-30 5:11 ` [net-next 06/15] net/mlx5: Generalize name of UMR alignment definition Saeed Mahameed
2022-11-30 5:11 ` [net-next 07/15] net/mlx5: Use generic definition for UMR KLM alignment Saeed Mahameed
2022-11-30 5:11 ` [net-next 08/15] net/mlx5: Fix orthography errors in documentation Saeed Mahameed
2022-11-30 5:11 ` [net-next 09/15] net/mlx5e: Don't use termination table when redundant Saeed Mahameed
2022-11-30 5:11 ` [net-next 10/15] net/mlx5e: Don't access directly DMA device pointer Saeed Mahameed
2022-11-30 5:11 ` [net-next 11/15] net/mlx5e: Delete always true DMA check Saeed Mahameed
2022-11-30 5:11 ` [net-next 12/15] net/mlx5: Remove redundant check Saeed Mahameed
2022-11-30 5:11 ` [net-next 13/15] net/mlx5e: Do early return when setup vports dests for slow path flow Saeed Mahameed
2022-11-30 5:11 ` [net-next 14/15] net/mlx5e: TC, Add offload support for trap with additional actions Saeed Mahameed
2022-11-30 5:11 ` [net-next 15/15] net/mlx5e: Support devlink reload of IPsec core Saeed Mahameed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221130051152.479480-5-saeed@kernel.org \
--to=saeed@kernel$(echo .)org \
--cc=davem@davemloft$(echo .)net \
--cc=edumazet@google$(echo .)com \
--cc=gal@nvidia$(echo .)com \
--cc=kuba@kernel$(echo .)org \
--cc=netdev@vger$(echo .)kernel.org \
--cc=pabeni@redhat$(echo .)com \
--cc=saeedm@nvidia$(echo .)com \
--cc=tariqt@nvidia$(echo .)com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox