Subject: Re: [PATCH net-next v2] net: dsa: mv88e6xxx: implement USXGMII mode for mv88e6393x

From: Marek Behún <[email-masked]>
Date: Tue, 30 May 2023 15:54:01 +0200

On Mon, 29 May 2023 17:23:12 +0000
Michal Smulski <[email-masked]> wrote:

> If I understand this correctly, you are asking to create a function for USXGMII similar to:
> 
> static int mv88e6390_serdes_pcs_get_state_sgmii(struct mv88e6xxx_chip *chip,
> 	int port, int lane, struct phylink_link_state *state)
> 
> However, the datasheet for 88e6393x chips does not document any registers for USXGMII interface (as it does for SGMII). You can only see that 10G link is valid by looking at MV88E6390_10G_STAT1 & MDIO_STAT1_LSTATUS which has already been implemented in:
> static int mv88e6390_serdes_pcs_get_state_10g(struct mv88e6xxx_chip *chip,
> 	int port, int lane, struct phylink_link_state *state)
> The datasheet states that in USXGMII mode the link is always set to 10GBASE-R coding for all data rates.
> 
> From the logs, I see that that the link is configured using in-band information. However, there is no register access in MV88E6393x that would allow to either control or get status information (speed, duplex, flow control, auto-negotiation, etc). Most of "useful" registers are already defined in mv88e6xxx/serdes.h file.
> 
> [   50.624175] mv88e6085 0x0000000008b96000:02: configuring for inband/usxgmii link mode
> ...
> [  387.116463] fsl_dpaa2_eth dpni.3 eth1: configuring for inband/usxgmii link mode
> [  387.132554] fsl_dpaa2_eth dpni.3 eth1: Link is Up - 10Gbps/Full - flow control off
> 
> If I misunderstood what is requested, please give me a bit more information what I should be adding for this patch to be accepted.

I know that 6393x does not document the USXGMII registers, but I bet
there are there. Similar to how 88X3540 supports USXGMII but the
registers are not documented.

Do you have func spec for 88X3310 / 88X3340 ? Those two document some
USXGMII registers, and the bits are the same as in this microsemi
document
  https://www.microsemi.com/document-portal/doc_view/1245324-coreusxgmii-hb

I don't acutally have access to Cisco's USXGMII specification, but I
bet these register bits are same between vendors. Could you at least
try to investigate this?

Marek