Subject: Re: QUSGMII control word

From: Maxime Chevallier <[email-masked]>
Date: Mon, 5 Jun 2023 08:13:34 +0200

Hello Russell,

On Fri, 2 Jun 2023 13:18:03 +0100
"Russell King (Oracle)" <[email-masked]> wrote:

> Hi Maxime,
> 
> Looking at your commit which introduced QUSGMII -
> 5e61fe157a27 ("net: phy: Introduce QUSGMII PHY mode"), are you sure
> your decoding of the control word is correct?
> 
> I've found some information online which suggests that QUSGMII uses a
> slightly different format to the control word from SGMII. Most of the
> bits are the same, but the speed bits occupy the three bits from 11:9,
> and 10M, 100M and 1G are encoded using bits 10:9, whereas in SGMII
> they are bits 11:10. In other words, in QUSGMII they are shifted one
> bit down. In your commit, you used the SGMII decoder for QUSGMII,
> which would mean we'd be picking out the wrong bits for decoding the
> speed.
> 
> QUSGMII also introduces EEE information into bits 8 and 7 whereas
> these are reserved in SGMII.
> 
> Please could you take a look, because I think we need a different
> decoder for the QUSGMII speed bits.

I've taken a look at it, back when I sent that patch I didn't have
access to the full documentation and used a vendor reference
implementation as a basis... I managed to get my hands on the proper
doc and the control word being used looks to be the usxgmii control
word, which matches with the offset you are seeing.

Do you have a patch or should I send a followup ?

Out of curiosity, on which hardware did you find this ?

I still have some patches of PCH extensions around, but didn't get any
room in my schedule to move forward with it. Is it something that you
plan on using ?

Thanks for the report,

Maxime

> Thanks.