Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property 'xlnx,has-ecc'

From: Rob Herring <[email-masked]>
Date: Mon, 28 Aug 2023 10:43:09 -0500

On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote:
> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller.
> Part of this feature configuration and counter registers added in
> IP for 1bit/2bit ECC errors.
> 
> xlnx,has-ecc is optional property and added to Xilinx AXI CAN Controller
> node if ECC block enabled in the HW
> 
> Signed-off-by: Srinivas Goud <[email-masked]>
> ---
> Changes in v3:
> Update commit description
> 
> Changes in v2:
> None

Doesn't apply, dependency?

> 
>  Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> index 64d57c3..c842610 100644
> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml
> @@ -49,6 +49,10 @@ properties:
>    resets:
>      maxItems: 1
>  
> +  xlnx,has-ecc:
> +    $ref: /schemas/types.yaml#/definitions/flag
> +    description: CAN Tx and Rx fifo ECC enable flag (AXI CAN)

has ECC or enable ECC?

> +
>  required:
>    - compatible
>    - reg
> @@ -137,6 +141,7 @@ examples:
>          interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
>          tx-fifo-depth = <0x40>;
>          rx-fifo-depth = <0x40>;
> +        xlnx,has-ecc

Obviously not tested.

>      };
>    - |
> -- 
> 2.1.1