Subject: Re: [net-next PATCH] net: phy: aquantia: make mailbox interface4 lsw addr mask more specific

From: Jakub Kicinski <[email-masked]>
Date: Tue, 21 Nov 2023 15:39:18 -0800

On Wed, 22 Nov 2023 00:32:56 +0100 Christian Marangi wrote:
> the 2 addr comes from a define
> 
> #define DRAM_BASE_ADDR		0x3FFE0000
> #define IRAM_BASE_ADDR		0x40000000
> 
> it wasn't clear to me if on BE these addrs gets saved differently or
> not. PHY wants the addr in LE.
> 
> On testing by removing the cpu_to_le32 the error is correctly removed!
> 
> I guess on BE the addr was actually swapped and FIELD_GET was correctly
> warning (and failing) as data was missing in applying the mask.

I think so. It's the responsibility of whether underlies 
phy_write_mmd() to make sure the data is put on the bus in
correct order (but that's still just within the u16 boundaries,
splitting a constant into u16 halves is not endian dependent).

> If all of this makes sense, will send a followup patch that drop the
> cpu_to_le32 and also the other in the bottom that does cpu_to_be32 (to a
> __swab32 as FW is LE and mailbox calculate CRC in BE)

Not so sure about this one, it puts the u32 on the stack, and takes 
the address of it:

	u32 word;

	word = (__force u32)cpu_to_be32(word);
	crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));

so the endian will matter here. My guess is that this part is correct.