Subject: Re: [PATCH v6 3/7] misc: Add support for LAN966x PCI device

From: Herve Codina <[email-masked]>
Date: Wed, 2 Oct 2024 18:02:07 +0200

On Wed, 02 Oct 2024 14:31:13 +0000
"Arnd Bergmann" <[email-masked]> wrote:

> On Wed, Oct 2, 2024, at 12:41, Herve Codina wrote:
> > On Wed, 02 Oct 2024 11:08:15 +0000
> > "Arnd Bergmann" <[email-masked]> wrote:  
> >> On Mon, Sep 30, 2024, at 12:15, Herve Codina wrote:
> >>   
> >> > +			pci-ep-bus@0 {
> >> > +				compatible = "simple-bus";
> >> > +				#address-cells = <1>;
> >> > +				#size-cells = <1>;
> >> > +
> >> > +				/*
> >> > +				 * map @0xe2000000 (32MB) to BAR0 (CPU)
> >> > +				 * map @0xe0000000 (16MB) to BAR1 (AMBA)
> >> > +				 */
> >> > +				ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
> >> > +				          0xe0000000 0x01 0x00 0x00 0x1000000>;    
> >> 
> >> I was wondering about how this fits into the PCI DT
> >> binding, is this a child of the PCI device, or does the
> >> "pci-ep-bus" refer to the PCI device itself?  
> >
> > This is a child of the PCI device.
> > The overlay is applied at the PCI device node and so, the pci-ep-bus is
> > a child of the PCI device node.  
> 
> Ok
> 
> > 				/*
> > 				 * Ranges items allow to reference BAR0,
> > 				 * BAR1, ... from children nodes.
> > 				 * The property is created by the PCI core
> > 				 * during the PCI bus scan.
> > 				 */
> > 				ranges = <0x00 0x00 0x00 0x82010000 0x00 0xe8000000 0x00 0x2000000
> > 					  0x01 0x00 0x00 0x82010000 0x00 0xea000000 0x00 0x1000000
> > 					  0x02 0x00 0x00 0x82010000 0x00 0xeb000000 0x00 0x800000  
> 
> >
> > Hope this full picture helped to understand the address translations
> > involved.  
> 
> Right, that makes a lot of sense now, I wasn't aware of those
> range properties getting set. Now I have a new question though:
> 
> Is this designed to work both on hosts using devicetree and on
> those not using it? If this is used on devicetree on a board
> that has a hardwired lan966x, we may want to include the
> overlay contents in the board dts file itself in order to
> describe any possible connections between the lan966x chip
> and other onboard components such as additional GPIOs or
> ethernet PHY chips, right?
> 
>       Arnd

On host with the base hardware described without device-tree (ACPI on
x86 for instance), I have a couple of patches not yet sent upstream.
With those patches, I have a the LAN966x PCI board working on x86.
I plan to send them as soon as this series is applied.

Rob said that before looking at ACPI, we need to have a working system
on DT based systems.
  https://lore.kernel.org/all/CAL_JsqKNC1Qv+fucobnzoXmxUYNockWR=[email-masked]/

If hardwired on a board, the same LAN966x PCI driver could be used.
A possible improvement of the driver could be to request the overlay
from the user-space using request_firmware().
With that, the overlay can be extended with specific onboard parts the
LAN966x PCI device is connected to.

This improvement can be done later when the use case appears.

Best regards,
Hervé