Subject: Re: [net-next PATCH v2 1/6] octeontx2: Set appropriate PF, VF masks and shifts based on silicon

From: Simon Horman <[email-masked]>
Date: Fri, 1 Nov 2024 10:08:32 +0000

On Wed, Oct 23, 2024 at 12:24:05AM +0530, Sai Krishna wrote:
> From: Subbaraya Sundeep <[email-masked]>
> 
> Number of RVU PFs on CN20K silicon have increased to 96 from maximum
> of 32 that were supported on earlier silicons. Every RVU PF and VF is
> identified by HW using a 16bit PF_FUNC value. Due to the change in
> Max number of PFs in CN20K, the bit encoding of this PF_FUNC has changed.
> 
> This patch handles the change by exporting PF,VF masks and shifts
> present in mailbox module to all other modules.
> 
> Also moved the NIX AF register offset macros to other files which
> will be posted in coming patches.
> 
> Signed-off-by: Subbaraya Sundeep <[email-masked]>
> Signed-off-by: Sai Krishna <[email-masked]>

...

> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> index 5016ba82e142..938a911cbf1c 100644
> --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
> @@ -41,10 +41,10 @@
>  #define MAX_CPT_BLKS				2
>  
>  /* PF_FUNC */
> -#define RVU_PFVF_PF_SHIFT	10
> -#define RVU_PFVF_PF_MASK	0x3F
> -#define RVU_PFVF_FUNC_SHIFT	0
> -#define RVU_PFVF_FUNC_MASK	0x3FF
> +#define RVU_PFVF_PF_SHIFT	rvu_pcifunc_pf_shift
> +#define RVU_PFVF_PF_MASK	rvu_pcifunc_pf_mask
> +#define RVU_PFVF_FUNC_SHIFT	rvu_pcifunc_func_shift
> +#define RVU_PFVF_FUNC_MASK	rvu_pcifunc_func_mask

Hi Subbaraya and Sai,

I see that this is in keeping with the implementation prior to this patch.
But, FWIIW, if FIELD_PREP() and friends were used then I expect the _SHIFT
defines could be removed entirely.

Please consider as a follow-up at some point.

>  #ifdef CONFIG_DEBUG_FS
>  struct dump_ctx {

...