Subject: Re: [PATCH net-next v3 0/2] net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX

From: Simon Horman <[email-masked]>
Date: Tue, 12 Nov 2024 14:08:33 +0000

+ Ido and Guilliame

On Sat, Nov 09, 2024 at 01:00:06PM +0200, Roger Quadros wrote:
> Configure DSCP to Priority mapping registers so that IP precedence
> field (top 3 bits of DSCP) map it to one of the 8 priority queues
> for RX traffic.
>     
> Also update Priority to Thread maping to be compliant with
> IEEE802.1Q-2014. Priority Code Point (PCP) 2 is higher priority than
> PCP 0 (Best Effort). PCP 1 (Background) is lower priority than
> PCP 0 (Best Effort).
> 
> Signed-off-by: Roger Quadros <[email-masked]>

Hi Ido and Guilliame,

I am wondering if you could find time to review this series.

> ---
> Changes in v3:
> - Added Reviewed-by tag to patch 1
> - Added macros for DSCP PRI field size and DSCP PRI per register
> - Drop unnecessary readl() in am65_cpsw_port_set_dscp_map()
> - Link to v2: https://lore.kernel.org/r/[email-masked]
> 
> Changes in v2:
> - Updated references to more recent standard IEEE802.1Q-2014.
> - Dropped reference to web link which might change in the future.
> - Typo fix in commit log.
> - Link to v1: https://lore.kernel.org/r/[email-masked]
> 
> ---
> Roger Quadros (2):
>       net: ethernet: ti: am65-cpsw: update pri_thread_map as per IEEE802.1Q-2014
>       net: ethernet: ti: am65-cpsw: enable DSCP to priority map for RX
> 
>  drivers/net/ethernet/ti/am65-cpsw-nuss.c | 54 ++++++++++++++++++++++++++++++++
>  drivers/net/ethernet/ti/cpsw_ale.c       | 36 ++++++++++++---------
>  2 files changed, 76 insertions(+), 14 deletions(-)
> ---
> base-commit: 42f7652d3eb527d03665b09edac47f85fb600924
> change-id: 20241101-am65-cpsw-multi-rx-dscp-000b2c4af6d0
> 
> Best regards,
> -- 
> Roger Quadros <[email-masked]>
>