Subject: Re: [PATCH net-next 2/2] net: phy: dp83822: Add support for GPIO2 clock output

From: Dimitri Fedrau <[email-masked]>
Date: Mon, 9 Dec 2024 14:52:05 +0100

Am Mon, Dec 09, 2024 at 02:17:04PM +0100 schrieb Andrew Lunn:
> >  #define MII_DP83822_RCSR	0x17
> >  #define MII_DP83822_RESET_CTRL	0x1f
> >  #define MII_DP83822_GENCFG	0x465
> > +#define MII_DP83822_IOCTRL2	0x463
> >  #define MII_DP83822_SOR1	0x467
> 
> These are sorted, so the MII_DP83822_IOCTRL2 should go before
> MII_DP83822_GENCFG.
>
Will fix it.

> > +	if (dp83822->set_gpio2_clk_out)
> > +		phy_modify_mmd(phydev, DP83822_DEVADDR, MII_DP83822_IOCTRL2,
> 
> I would of preferred MDIO_MMD_VEND2 rather than DP83822_DEVADDR, but
> having just this one instance correct would look a bit odd.
>
Is it worth fixing it in a separate patch, replacing all DP83822_DEVADDR
with MDIO_MMD_VEND2 ?

> > +	ret = of_property_read_u32(dev->of_node, "ti,gpio2-clk-out",
> > +				   &dp83822->gpio2_clk_out);
> > +	if (!ret) {
> > +		dp83822->set_gpio2_clk_out = true;
> > +		switch (dp83822->gpio2_clk_out) {
> > +		case DP83822_CLK_SRC_MAC_IF:
> > +			break;
> > +		case DP83822_CLK_SRC_XI:
> > +			break;
> > +		case DP83822_CLK_SRC_INT_REF:
> > +			break;
> > +		case DP83822_CLK_SRC_RMII_MASTER_MODE_REF:
> > +			break;
> > +		case DP83822_CLK_SRC_FREE_RUNNING:
> > +			break;
> > +		case DP83822_CLK_SRC_RECOVERED:
> > +			break;
> 
> You can list multiple case statements together, and have one break at
> the end.
> 
Will fix it.

> I would personally also only have:
> 
> > +		dp83822->set_gpio2_clk_out = true;
> 
> if validation passes, not that it really matters because:
> 
> 
> > +		default:
> > +			phydev_err(phydev, "ti,gpio2-clk-out value %u not valid\n",
> > +				   dp83822->gpio2_clk_out);
> > +			return -EINVAL;
> > +		}
> > +	}
> 
Ok.

	Dimitri