Subject: Re: [PATCH v8 16/27] sfc: obtain root decoder with enough HPA free space

From: kernel test robot <[email-masked]>
Date: Thu, 26 Dec 2024 04:21:30 +0800

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on fac04efc5c793dccbd07e2d59af9f90b7fc0dca4]

url:    https://github.com/intel-lab-lkp/linux/commits/alejandro-lucero-palau-amd-com/cxl-add-type2-device-basic-support/20241217-001923
base:   fac04efc5c793dccbd07e2d59af9f90b7fc0dca4
patch link:    https://lore.kernel.org/r/20241216161042.42108-17-alejandro.lucero-palau%40amd.com
patch subject: [PATCH v8 16/27] sfc: obtain root decoder with enough HPA free space
config: x86_64-randconfig-071-20241225 (https://download.01.org/0day-ci/archive/20241226/[email-masked]/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241226/[email-masked]/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email-masked]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email-masked]/

All errors (new ones prefixed by >>):

   ld: drivers/net/ethernet/sfc/efx_cxl.o: in function `efx_cxl_init':
>> drivers/net/ethernet/sfc/efx_cxl.c:107: undefined reference to `cxl_get_hpa_freespace'

vim +107 drivers/net/ethernet/sfc/efx_cxl.c

    20	
    21	int efx_cxl_init(struct efx_probe_data *probe_data)
    22	{
    23		struct efx_nic *efx = &probe_data->efx;
    24		DECLARE_BITMAP(expected, CXL_MAX_CAPS);
    25		DECLARE_BITMAP(found, CXL_MAX_CAPS);
    26		resource_size_t max_size;
    27		struct pci_dev *pci_dev;
    28		struct efx_cxl *cxl;
    29		struct resource res;
    30		u16 dvsec;
    31		int rc;
    32	
    33		pci_dev = efx->pci_dev;
    34		probe_data->cxl_pio_initialised = false;
    35	
    36		dvsec = pci_find_dvsec_capability(pci_dev, PCI_VENDOR_ID_CXL,
    37						  CXL_DVSEC_PCIE_DEVICE);
    38		if (!dvsec)
    39			return 0;
    40	
    41		pci_dbg(pci_dev, "CXL_DVSEC_PCIE_DEVICE capability found\n");
    42	
    43		cxl = kzalloc(sizeof(*cxl), GFP_KERNEL);
    44		if (!cxl)
    45			return -ENOMEM;
    46	
    47		cxl->cxlds = cxl_accel_state_create(&pci_dev->dev);
    48		if (IS_ERR(cxl->cxlds)) {
    49			pci_err(pci_dev, "CXL accel device state failed");
    50			rc = -ENOMEM;
    51			goto err_state;
    52		}
    53	
    54		cxl_set_dvsec(cxl->cxlds, dvsec);
    55		cxl_set_serial(cxl->cxlds, pci_dev->dev.id);
    56	
    57		res = DEFINE_RES_MEM(0, EFX_CTPIO_BUFFER_SIZE);
    58		if (cxl_set_resource(cxl->cxlds, res, CXL_RES_DPA)) {
    59			pci_err(pci_dev, "cxl_set_resource DPA failed\n");
    60			rc = -EINVAL;
    61			goto err_resource_set;
    62		}
    63	
    64		res = DEFINE_RES_MEM_NAMED(0, EFX_CTPIO_BUFFER_SIZE, "ram");
    65		if (cxl_set_resource(cxl->cxlds, res, CXL_RES_RAM)) {
    66			pci_err(pci_dev, "cxl_set_resource RAM failed\n");
    67			rc = -EINVAL;
    68			goto err_resource_set;
    69		}
    70	
    71		rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds);
    72		if (rc) {
    73			pci_err(pci_dev, "CXL accel setup regs failed");
    74			goto err_resource_set;
    75		}
    76	
    77		bitmap_clear(expected, 0, CXL_MAX_CAPS);
    78		bitmap_set(expected, CXL_DEV_CAP_HDM, 1);
    79		bitmap_set(expected, CXL_DEV_CAP_RAS, 1);
    80	
    81		if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) {
    82			pci_err(pci_dev,
    83				"CXL device capabilities found(%08lx) not as expected(%08lx)",
    84				*found, *expected);
    85			rc = -EIO;
    86			goto err_resource_set;
    87		}
    88	
    89		rc = cxl_request_resource(cxl->cxlds, CXL_RES_RAM);
    90		if (rc) {
    91			pci_err(pci_dev, "CXL request resource failed");
    92			goto err_resource_set;
    93		}
    94	
    95		/* We do not have the register about media status. Hardware design
    96		 * implies it is ready.
    97		 */
    98		cxl_set_media_ready(cxl->cxlds);
    99	
   100		cxl->cxlmd = devm_cxl_add_memdev(&pci_dev->dev, cxl->cxlds);
   101		if (IS_ERR(cxl->cxlmd)) {
   102			pci_err(pci_dev, "CXL accel memdev creation failed");
   103			rc = PTR_ERR(cxl->cxlmd);
   104			goto err_memdev;
   105		}
   106	
 > 107		cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd,
   108						   CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2,
   109						   &max_size);
   110	
   111		if (IS_ERR(cxl->cxlrd)) {
   112			pci_err(pci_dev, "cxl_get_hpa_freespace failed\n");
   113			rc = PTR_ERR(cxl->cxlrd);
   114			goto err_memdev;
   115		}
   116	
   117		if (max_size < EFX_CTPIO_BUFFER_SIZE) {
   118			pci_err(pci_dev, "%s: not enough free HPA space %pap < %u\n",
   119				__func__, &max_size, EFX_CTPIO_BUFFER_SIZE);
   120			rc = -ENOSPC;
   121			goto err_memdev;
   122		}
   123	
   124		probe_data->cxl = cxl;
   125	
   126		return 0;
   127	
   128	err_memdev:
   129		cxl_release_resource(cxl->cxlds, CXL_RES_RAM);
   130	err_resource_set:
   131		kfree(cxl->cxlds);
   132	err_state:
   133		kfree(cxl);
   134		return rc;
   135	}
   136	

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