Subject: Re: [PATCH V2 net 4/4] net: hns3: default enable tx bounce buffer when smmu enabled

From: Simon Horman <[email-masked]>
Date: Wed, 23 Jul 2025 08:29:00 +0100

On Tue, Jul 22, 2025 at 08:54:23PM +0800, Jijie Shao wrote:
> The SMMU engine on HIP09 chip has a hardware issue.
> SMMU pagetable prefetch features may prefetch and use a invalid PTE
> even the PTE is valid at that time. This will cause the device trigger
> fake pagefaults. The solution is to avoid prefetching by adding a
> SYNC command when smmu mapping a iova. But the performance of nic has a
> sharp drop. Then we do this workaround, always enable tx bounce buffer,
> avoid mapping/unmapping on TX path.
> 
> This issue only affects HNS3, so we always enable
> tx bounce buffer when smmu enabled to improve performance.
> 
> Fixes: 295ba232a8c3 ("net: hns3: add device version to replace pci revision")
> Signed-off-by: Jian Shen <[email-masked]>
> Signed-off-by: Jijie Shao <[email-masked]>
> ---
> ChangeLog:
> v1 -> v2:
>   - Split this patch, omits the ethtool changes,
>     ethtool changes will be sent to net-next, suggested by Simon Horman
>   v1: https://lore.kernel.org/all/[email-masked]/

Thanks for breaking this out.

Reviewed-by: Simon Horman <[email-masked]>