Subject: [PATCH net-next] net: usb: sr9700: clarify code using BIT and GENMASK macros

From: Ethan Nelson-Moore <[email-masked]>
Date: Fri, 23 Jan 2026 20:02:20 -0800

The sr9700 driver contains many hardcoded bit shifts and masks. Make
the code clearer and adhere to the kernel code style by replacing them
with the equivalent BIT and GENMASK macros. Also take the opportunity
to align some indentation.

To avoid merge conflicts, code which is removed by other pending
patches is not modified.

Signed-off-by: Ethan Nelson-Moore <[email-masked]>
---
 drivers/net/usb/sr9700.h | 144 +++++++++++++++++++--------------------
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/drivers/net/usb/sr9700.h b/drivers/net/usb/sr9700.h
index 3212859830dc..71a9d2335126 100644
--- a/drivers/net/usb/sr9700.h
+++ b/drivers/net/usb/sr9700.h
@@ -12,93 +12,93 @@
 
 /* Network Control Reg */
 #define	SR_NCR			0x00
-#define		NCR_RST			(1 << 0)
-#define		NCR_LBK			(3 << 1)
-#define		NCR_FDX			(1 << 3)
-#define		NCR_WAKEEN		(1 << 6)
+#define		NCR_RST			BIT(0)
+#define		NCR_LBK			GENMASK(2, 1)
+#define		NCR_FDX			BIT(3)
+#define		NCR_WAKEEN		BIT(6)
 /* Network Status Reg */
 #define	SR_NSR			0x01
-#define		NSR_RXRDY		(1 << 0)
-#define		NSR_RXOV		(1 << 1)
-#define		NSR_TX1END		(1 << 2)
-#define		NSR_TX2END		(1 << 3)
-#define		NSR_TXFULL		(1 << 4)
-#define		NSR_WAKEST		(1 << 5)
-#define		NSR_LINKST		(1 << 6)
-#define		NSR_SPEED		(1 << 7)
+#define		NSR_RXRDY		BIT(0)
+#define		NSR_RXOV		BIT(1)
+#define		NSR_TX1END		BIT(2)
+#define		NSR_TX2END		BIT(3)
+#define		NSR_TXFULL		BIT(4)
+#define		NSR_WAKEST		BIT(5)
+#define		NSR_LINKST		BIT(6)
+#define		NSR_SPEED		BIT(7)
 /* Tx Control Reg */
 #define	SR_TCR			0x02
-#define		TCR_CRC_DIS		(1 << 1)
-#define		TCR_PAD_DIS		(1 << 2)
-#define		TCR_LC_CARE		(1 << 3)
-#define		TCR_CRS_CARE	(1 << 4)
-#define		TCR_EXCECM		(1 << 5)
-#define		TCR_LF_EN		(1 << 6)
+#define		TCR_CRC_DIS		BIT(1)
+#define		TCR_PAD_DIS		BIT(2)
+#define		TCR_LC_CARE		BIT(3)
+#define		TCR_CRS_CARE		BIT(4)
+#define		TCR_EXCECM		BIT(5)
+#define		TCR_LF_EN		BIT(6)
 /* Tx Status Reg for Packet Index 1 */
 #define	SR_TSR1		0x03
-#define		TSR1_EC			(1 << 2)
-#define		TSR1_COL		(1 << 3)
-#define		TSR1_LC			(1 << 4)
-#define		TSR1_NC			(1 << 5)
-#define		TSR1_LOC		(1 << 6)
-#define		TSR1_TLF		(1 << 7)
+#define		TSR1_EC			BIT(2)
+#define		TSR1_COL		BIT(3)
+#define		TSR1_LC			BIT(4)
+#define		TSR1_NC			BIT(5)
+#define		TSR1_LOC		BIT(6)
+#define		TSR1_TLF		BIT(7)
 /* Tx Status Reg for Packet Index 2 */
 #define	SR_TSR2		0x04
-#define		TSR2_EC			(1 << 2)
-#define		TSR2_COL		(1 << 3)
-#define		TSR2_LC			(1 << 4)
-#define		TSR2_NC			(1 << 5)
-#define		TSR2_LOC		(1 << 6)
-#define		TSR2_TLF		(1 << 7)
+#define		TSR2_EC			BIT(2)
+#define		TSR2_COL		BIT(3)
+#define		TSR2_LC			BIT(4)
+#define		TSR2_NC			BIT(5)
+#define		TSR2_LOC		BIT(6)
+#define		TSR2_TLF		BIT(7)
 /* Rx Control Reg*/
 #define	SR_RCR			0x05
-#define		RCR_RXEN		(1 << 0)
-#define		RCR_PRMSC		(1 << 1)
-#define		RCR_RUNT		(1 << 2)
-#define		RCR_ALL			(1 << 3)
-#define		RCR_DIS_CRC		(1 << 4)
-#define		RCR_DIS_LONG	(1 << 5)
+#define		RCR_RXEN		BIT(0)
+#define		RCR_PRMSC		BIT(1)
+#define		RCR_RUNT		BIT(2)
+#define		RCR_ALL			BIT(3)
+#define		RCR_DIS_CRC		BIT(4)
+#define		RCR_DIS_LONG		BIT(5)
 /* Rx Status Reg */
 #define	SR_RSR			0x06
-#define		RSR_AE			(1 << 2)
-#define		RSR_MF			(1 << 6)
-#define		RSR_RF			(1 << 7)
+#define		RSR_AE			BIT(2)
+#define		RSR_MF			BIT(6)
+#define		RSR_RF			BIT(7)
 /* Rx Overflow Counter Reg */
-#define	SR_ROCR		0x07
-#define		ROCR_ROC		(0x7F << 0)
-#define		ROCR_RXFU		(1 << 7)
+#define	SR_ROCR			0x07
+#define		ROCR_ROC		GENMASK(6, 0)
+#define		ROCR_RXFU		BIT(7)
 /* Back Pressure Threshold Reg */
-#define	SR_BPTR		0x08
-#define		BPTR_JPT		(0x0F << 0)
-#define		BPTR_BPHW		(0x0F << 4)
+#define	SR_BPTR			0x08
+#define		BPTR_JPT		GENMASK(3, 0)
+#define		BPTR_BPHW		GENMASK(7, 4)
 /* Flow Control Threshold Reg */
-#define	SR_FCTR		0x09
-#define		FCTR_LWOT		(0x0F << 0)
-#define		FCTR_HWOT		(0x0F << 4)
+#define	SR_FCTR			0x09
+#define		FCTR_LWOT		GENMASK(3, 0)
+#define		FCTR_HWOT		GENMASK(7, 4)
 /* rx/tx Flow Control Reg */
 #define	SR_FCR			0x0A
-#define		FCR_FLCE		(1 << 0)
-#define		FCR_BKPA		(1 << 4)
-#define		FCR_TXPEN		(1 << 5)
-#define		FCR_TXPF		(1 << 6)
-#define		FCR_TXP0		(1 << 7)
+#define		FCR_FLCE		BIT(0)
+#define		FCR_BKPA		BIT(4)
+#define		FCR_TXPEN		BIT(5)
+#define		FCR_TXPF		BIT(6)
+#define		FCR_TXP0		BIT(7)
 /* Eeprom Control Reg */
-#define	SR_EPCR		0x0B
-#define		EPCR_ERRE		(1 << 0)
-#define		EPCR_ERPRW		(1 << 1)
-#define		EPCR_ERPRR		(1 << 2)
-#define		EPCR_WEP		(1 << 4)
+#define	SR_EPCR			0x0B
+#define		EPCR_ERRE		BIT(0)
+#define		EPCR_ERPRW		BIT(1)
+#define		EPCR_ERPRR		BIT(2)
+#define		EPCR_WEP		BIT(4)
 /* Eeprom Address Reg */
-#define	SR_EPAR		0x0C
-#define		EPAR_EROA		(0x3F << 0)
+#define	SR_EPAR			0x0C
+#define		EPAR_EROA		GENMASK(5, 0)
 /* Eeprom Data Reg */
 #define	SR_EPDR		0x0D	/* 0x0D ~ 0x0E for Data Reg Low & High */
 /* Wakeup Control Reg */
 #define	SR_WCR			0x0F
-#define		WCR_MAGICST		(1 << 0)
-#define		WCR_LINKST		(1 << 2)
-#define		WCR_MAGICEN		(1 << 3)
-#define		WCR_LINKEN		(1 << 5)
+#define		WCR_MAGICST		BIT(0)
+#define		WCR_LINKST		BIT(2)
+#define		WCR_MAGICEN		BIT(3)
+#define		WCR_LINKEN		BIT(5)
 /* Physical Address Reg */
 #define	SR_PAR			0x10	/* 0x10 ~ 0x15 6 bytes for PAR */
 /* Multicast Address Reg */
@@ -106,7 +106,7 @@
 /* 0x1e unused */
 /* Phy Reset Reg */
 #define	SR_PRR			0x1F
-#define		PRR_PHY_RST		(1 << 0)
+#define		PRR_PHY_RST		BIT(0)
 /* Tx sdram Write Pointer Address Low */
 #define	SR_TWPAL		0x20
 /* Tx sdram Write Pointer Address High */
@@ -132,17 +132,17 @@
 /* 0x2D --> 0xEF unused */
 /* USB Device Address */
 #define	SR_USBDA		0xF0
-#define		USBDA_USBFA		(0x7F << 0)
+#define		USBDA_USBFA		GENMASK(6, 0)
 /* RX packet Counter Reg */
 #define	SR_RXC			0xF1
 /* Tx packet Counter & USB Status Reg */
 #define	SR_TXC_USBS		0xF2
-#define		TXC_USBS_TXC0		(1 << 0)
-#define		TXC_USBS_TXC1		(1 << 1)
-#define		TXC_USBS_TXC2		(1 << 2)
-#define		TXC_USBS_EP1RDY		(1 << 5)
-#define		TXC_USBS_SUSFLAG	(1 << 6)
-#define		TXC_USBS_RXFAULT	(1 << 7)
+#define		TXC_USBS_TXC0		BIT(0)
+#define		TXC_USBS_TXC1		BIT(1)
+#define		TXC_USBS_TXC2		BIT(2)
+#define		TXC_USBS_EP1RDY		BIT(5)
+#define		TXC_USBS_SUSFLAG	BIT(6)
+#define		TXC_USBS_RXFAULT	BIT(7)
 /* USB Control register */
 #define	SR_USBC			0xF4
 #define		USBC_EP3NAK		(1 << 4)
-- 
2.43.0