Subject: Re: [PATCH net-next v3 1/2] dpll: add fractional frequency offset to pin-parent-device

From: Jakub Kicinski <[email-masked]>
Date: Wed, 6 May 2026 18:33:42 -0700

On Mon,  4 May 2026 17:53:39 +0200 Ivan Vecera wrote:
> +          At top level this represents the RX vs TX symbol rate
> +          offset on the media associated with the pin.

Isn't this a hacky hack? I'd think that pin is in or out.
Having a freq offset between two pins or pin and parent's
ref lock makes sense. This new interpretation sounds like
we are trying to shove a difference between two pins into one?

> @@ -299,6 +299,10 @@ zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv,
>  {
>  	struct zl3073x_dpll_pin *pin = pin_priv;
>  
> +	/* Only rx vs tx symbol rate FFO is supported */
> +	if (dpll)
> +		return -ENODATA;
> +
>  	*ffo = pin->freq_offset;

It's easy for driver authors to forget this sort of validation.
We should fail close, so it's better to have some "capability"
bits or something for the driver to opt into getting given format 
of the call.