From: Florian Fainelli <f.fainelli@gmail•com>
To: Russell King - ARM Linux <linux@armlinux•org.uk>,
Andrew Lunn <andrew@lunn•ch>
Cc: netdev@vger•kernel.org
Subject: Re: [PATCH 2/5] net: phy: hook up clause 45 autonegotiation restart
Date: Thu, 1 Jun 2017 10:16:17 -0700 [thread overview]
Message-ID: <23c238e0-2af8-3171-9986-af02e9c19129@gmail.com> (raw)
In-Reply-To: <20170601162417.GA14541@n2100.armlinux.org.uk>
On 06/01/2017 09:24 AM, Russell King - ARM Linux wrote:
> On Thu, Jun 01, 2017 at 04:47:35PM +0100, Russell King - ARM Linux wrote:
>> On Thu, Jun 01, 2017 at 03:19:55PM +0200, Andrew Lunn wrote:
>>> On Thu, Jun 01, 2017 at 02:09:00PM +0100, Russell King - ARM Linux wrote:
>>>> On Thu, Jun 01, 2017 at 03:05:27PM +0200, Andrew Lunn wrote:
>>>>> So you are saying a 10G PHY driver always needs to have a aneg_done
>>>>> callback, even if it just needs to call phygen_c45_aneg_done?
>>>>>
>>>>> This seems a bit error prone. I can see somebody writing a 10G driver,
>>>>> leaving out aneg_done() and having the c22 version called. Is the read
>>>>> of MII_BMSR likely to return 0xffff, since the register does not
>>>>> exist? If so, genphy_aneg_done() is likely to always return
>>>>> BMSR_ANEGCOMPLETE.
>>>>
>>>> Don't forget that the read will fail, so phy_read() will return a
>>>> negative number.
>>>
>>> By fail, you mean return something like -EIO or -ETIMEOUT? Is this
>>> guaranteed in the code somewhere? This particular Marvell PHY only
>>> does c45. But i could imagine some other PHYs answering a c22 request
>>> with 0xffff.
>>
>> Yes, C45 allows the PHYs to answer C22 as well, but then they have to
>> implement the C22 register set. Such a PHY would be out of spec,
>> especially as what you're suggesting is that it answers C22 cycles
>> and fails to implement MII_BMSR. I also think that there's a comment
>> in the 802.3 specs that says that unimplemented registers are to
>> return zero, not 0xffff.
>
> Checking 802.3-2015, in "22.2.4 Management functions", the first
> sentence requires all PHYs that respond to Clause 22 cycles to
> implement BMCR and BMSR. However, my statement about unimplemented
> registers returning zero seems to be a C45 thing, not a C22 thing,
> according to the C22 PICS and "45.2 MDIO Interface Registers"
>
> However, digging a bit further, "22.2.4.2.10 Auto-Negotiation complete"
> states that bit 5 shall be zero if aneg has not completed or if aneg is
> unimplemented.
>
So how about we are more defensive than that and if we are presented
with a C45 PHY driver that does not have an aneg_done() function pointer
set we return an error/warning during driver registration?
--
Florian
next prev parent reply other threads:[~2017-06-01 17:16 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-01 10:23 [PATCH 0/5] Add phylib support for MV88X3310 10G phy Russell King - ARM Linux
2017-06-01 10:26 ` [PATCH 1/5] net: phy: add 802.3 clause 45 support to phylib Russell King
2017-06-01 12:28 ` Andrew Lunn
2017-06-01 17:15 ` Florian Fainelli
2017-06-02 12:39 ` Russell King - ARM Linux
2017-06-01 10:26 ` [PATCH 2/5] net: phy: hook up clause 45 autonegotiation restart Russell King
2017-06-01 12:23 ` Andrew Lunn
2017-06-01 12:51 ` Russell King - ARM Linux
2017-06-01 13:05 ` Andrew Lunn
2017-06-01 13:09 ` Russell King - ARM Linux
2017-06-01 13:19 ` Andrew Lunn
2017-06-01 15:47 ` Russell King - ARM Linux
2017-06-01 16:24 ` Russell King - ARM Linux
2017-06-01 17:16 ` Florian Fainelli [this message]
2017-06-02 12:43 ` Russell King - ARM Linux
2017-06-02 13:46 ` Andrew Lunn
2017-06-02 14:04 ` Russell King - ARM Linux
2017-06-01 10:26 ` [PATCH 3/5] net: phy: split out 10G genphy support Russell King
2017-06-01 12:29 ` Andrew Lunn
2017-06-01 17:17 ` Florian Fainelli
2017-06-01 10:26 ` [PATCH 4/5] net: phy: add XAUI and 10GBASE-KR PHY connection types Russell King
[not found] ` <E1dGNJX-00043v-3M-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
2017-06-01 12:30 ` Andrew Lunn
2017-06-01 16:56 ` Florian Fainelli
[not found] ` <fb1a81e0-b5b9-80e4-7852-cc65a574b9e9-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-06-01 17:32 ` Russell King - ARM Linux
2017-06-01 10:26 ` [PATCH 5/5] net: phy: add Marvell Alaska X 88X3310 10Gigabit PHY support Russell King
2017-06-01 12:51 ` Andrew Lunn
2017-06-01 13:06 ` Russell King - ARM Linux
2017-06-01 17:28 ` Florian Fainelli
2017-06-01 17:57 ` Russell King - ARM Linux
2017-06-01 16:07 ` [PATCH 0/5] Add phylib support for MV88X3310 10G phy David Miller
[not found] ` <20170601.120736.670167741447008364.davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
2017-06-01 16:54 ` Russell King - ARM Linux
[not found] ` <20170601102327.GF27796-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
2017-06-05 11:22 ` [PATCH v2 0/6] " Russell King - ARM Linux
2017-06-05 11:22 ` [PATCH 1/6] net: phy: add 802.3 clause 45 support to phylib Russell King
2017-06-05 16:25 ` Florian Fainelli
2017-06-05 11:22 ` [PATCH 2/6] net: phy: avoid genphy_aneg_done() for PHYs without clause 22 support Russell King
2017-06-05 11:58 ` Andrew Lunn
2017-06-05 16:29 ` Florian Fainelli
2017-06-05 11:23 ` [PATCH 3/6] net: phy: hook up clause 45 autonegotiation restart Russell King
2017-06-05 11:59 ` Andrew Lunn
2017-06-05 16:30 ` Florian Fainelli
2017-06-05 11:23 ` [PATCH 4/6] net: phy: split out 10G genphy support Russell King
2017-06-05 11:23 ` [PATCH 5/6] net: phy: add XAUI and 10GBASE-KR PHY connection types Russell King
[not found] ` <E1dHq6I-0005XE-VR-eh5Bv4kxaXIk46pC+1QYvQNdhmdF6hFW@public.gmane.org>
2017-06-05 12:00 ` Andrew Lunn
2017-06-05 16:24 ` Florian Fainelli
2017-06-05 11:23 ` [PATCH 6/6] net: phy: add Marvell Alaska X 88X3310 10Gigabit PHY support Russell King
2017-06-05 18:20 ` Andrew Lunn
2017-06-05 18:21 ` Florian Fainelli
2017-06-05 18:21 ` Andrew Lunn
2017-06-05 22:10 ` Russell King - ARM Linux
[not found] ` <20170605112203.GA10680-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org>
2017-06-05 21:53 ` [PATCH v2 0/6] Add phylib support for MV88X3310 10G phy David Miller
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