Subject: Re: [PATCH 2/2] net/ibm/emac: wrong bit is used for STA control register write

From: Christian Lamparter <[email-masked]>
Date: Mon, 22 Jan 2018 17:22:30 +0100

On Monday, January 22, 2018 5:00:38 PM CET Ivan Mikhaylov wrote:
> STA control register has areas of mode and opcodes for opeations. 18 bit is
> using for mode selection, where 0 is old MIO/MDIO access method and 1 is
> indirect access mode. 19-20 bits are using for setting up read/write
> operation(STA opcodes). In current state 'read' is set into old MIO/MDIO mode
> with 19 bit and write operation is set into 18 bit which is mode selection,
> not a write operation. To correlate write with read we set it into 20 bit.
> 
> Signed-off-by: Ivan Mikhaylov <[email-masked]>
> ---
>  drivers/net/ethernet/ibm/emac/emac.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h
> index d0a0e3b..c26d263 100644
> --- a/drivers/net/ethernet/ibm/emac/emac.h
> +++ b/drivers/net/ethernet/ibm/emac/emac.h
> @@ -244,7 +244,7 @@ struct emac_regs {
>  #define EMAC_STACR_PHYE			0x00004000
>  #define EMAC_STACR_STAC_MASK		0x00003000
>  #define EMAC_STACR_STAC_READ		0x00001000
> -#define EMAC_STACR_STAC_WRITE		0x00002000
> +#define EMAC_STACR_STAC_WRITE		0x00000800
>  #define EMAC_STACR_OPBC_MASK		0x00000C00
>  #define EMAC_STACR_OPBC_50		0x00000000
>  #define EMAC_STACR_OPBC_66		0x00000400
> 

Something looks wrong here?! The commit message talks about bit 18, 19 and 20.
However, 0x0800, 0x1000, 0x2000 and are like bit 11, 12 and 13? Furthermore,
what about the EMAC_STACR_STAC_MASK? shouldn't it be 0x1800 now (or delete it
since it doesn't look like it's used anywhere?).