Subject: [PATCH] Merge GT/MV642xx Support into MV643xx Driver [1/8]

From: "Steven J. Hill" <[email-masked]>
Date: Wed, 18 Jul 2007 23:47:54 -0500

This first patch 642xx #defines to the 'include/linux/mv643xx.h' file.

Signed-off-by: Steven J. Hill <[email-masked]>
---

--- linux-2.6.22.1/include/linux/mv643xx.h	2007-05-10 15:16:24.000000000 -0500
+++ linux-2.6.22.1-rci/include/linux/mv643xx.h	2007-07-18 15:50:44.000000000 -0500
@@ -666,7 +666,11 @@
 #define MV643XX_ETH_SHARED_REGS_SIZE                                0x2000
 
 #define MV643XX_ETH_PHY_ADDR_REG                                    0x2000
+#ifdef CONFIG_GT64260
+#define MV643XX_ETH_SMI_REG                                         0x2010
+#else
 #define MV643XX_ETH_SMI_REG                                         0x2004
+#endif
 #define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG                           0x2008
 #define MV643XX_ETH_UNIT_DEFAULTID_REG                              0x200c
 #define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG                        0x2080
@@ -693,6 +697,21 @@
 #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3                           0x228c
 #define MV643XX_ETH_BASE_ADDR_ENABLE_REG                            0x2290
 #define MV643XX_ETH_ACCESS_PROTECTION_REG(port)                    (0x2294 + (port<<2))
+#ifdef CONFIG_GT64260
+#define MV643XX_ETH_PORT_CONFIG_REG(port)                          (0x2400 + (port<<10))
+#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port)                   (0x2408 + (port<<10))
+#define MV643XX_ETH_PORT_STATUS_REG(port)                          (0x2418 + (port<<10))
+#define GT64260_ETH_HASH_TABLE_POINTER_REG(port)                   (0x2428 + (port<<10))
+#define MV643XX_ETH_SDMA_CONFIG_REG(port)                          (0x2440 + (port<<10))
+#define MV643XX_ETH_SDMA_COMMAND_REG(port)                         (0x2448 + (port<<10))
+#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port)                      (0x2450 + (port<<10))
+#define MV643XX_ETH_INTERRUPT_MASK_REG(port)                       (0x2458 + (port<<10))
+#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port)            (0x2470 + (port<<10))
+#define MV643XX_ETH_RX_FIRST_QUEUE_DESC_PTR_0(port)                (0x2480 + (port<<10))
+#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x24a0 + (port<<10))
+#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port)              (0x24e0 + (port<<10))
+#define MV643XX_ETH_MIB_COUNTERS_BASE(port)                        (0x2500 + (port<<7))
+#else
 #define MV643XX_ETH_MIB_COUNTERS_BASE(port)                        (0x3000 + (port<<7))
 #define MV643XX_ETH_PORT_CONFIG_REG(port)                          (0x2400 + (port<<10))
 #define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port)                   (0x2404 + (port<<10))
@@ -775,6 +794,7 @@
 #define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port)   (0x3400 + (port<<10))
 #define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port)     (0x3500 + (port<<10))
 #define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port)             (0x3600 + (port<<10))
+#endif
 
 /*******************************************/
 /*          CUNIT  Registers               */
@@ -1094,6 +1114,45 @@
 };
 
 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
+#define GT64260_ETH_RECEIVE_BC			0
+#define GT64260_ETH_REJECT_BC			(1<<1)
+#define GT64260_ETH_REJECT_BAD_FRAMES		0
+#define GT64260_ETH_RECEIVE_BAD_FRAMES		(1<<2)
+#define GT64260_ETH_DISABLE			0
+#define GT64260_ETH_ENABLE			(1<<7)
+#define GT64260_ETH_CLR_INT_LOOPBACK		0
+#define GT64260_ETH_SET_INT_LOOPBACK		(1<<8)
+#define GT64260_ETH_CLR_EXT_LOOPBACK		0
+#define GT64260_ETH_SET_EXT_LOOPBACK		(1<<9)
+#define GT64260_ETH_DISABLE_FORCE_COLLISION	0
+#define GT64260_ETH_ENABLE_FORCE_COLLISION	(1<<10)
+#define GT64260_ETH_HASH_SIZE_HALFK		0
+#define GT64260_ETH_HASH_SIZE_8K		(1<<12)
+#define GT64260_ETH_HASH_SIZE_SHIFT		12
+#define GT64260_ETH_HASH_MODE_0			0
+#define GT64260_ETH_HASH_MODE_1			(1<<13)
+#define GT64260_ETH_HASH_MODE_SHIFT		13
+#define GT64260_ETH_HASH_DEFAULT_DISCARD	0
+#define GT64260_ETH_HASH_DEFAULT_PASS		(1<<14)
+#define GT64260_ETH_HASH_DEFAULT_SHIFT		14
+#define GT64260_ETH_SET_HALF_DUPLEX_MODE	0
+#define GT64260_ETH_SET_FULL_DUPLEX_MODE	(1<<15)
+#define GT64260_ETH_DISABLE_ACCEL_SLOT_TIME	0
+#define GT64260_ETH_ENABLE_ACCEL_SLOT_TIME	(1<<31)
+
+#define	GT64260_ETH_PORT_CONFIG_DEFAULT_VALUE			\
+		GT64260_ETH_RECEIVE_BC			|	\
+		GT64260_ETH_REJECT_BAD_FRAMES		|	\
+		GT64260_ETH_DISABLE			|	\
+		GT64260_ETH_CLR_INT_LOOPBACK		|	\
+		GT64260_ETH_CLR_EXT_LOOPBACK		|	\
+		GT64260_ETH_DISABLE_FORCE_COLLISION	|	\
+		GT64260_ETH_HASH_SIZE_HALFK		|	\
+		GT64260_ETH_HASH_MODE_0			|	\
+		GT64260_ETH_HASH_DEFAULT_DISCARD	|	\
+		GT64260_ETH_SET_FULL_DUPLEX_MODE	|	\
+		GT64260_ETH_DISABLE_ACCEL_SLOT_TIME
+
 #define MV643XX_ETH_UNICAST_NORMAL_MODE		0
 #define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE	(1<<0)
 #define MV643XX_ETH_DEFAULT_RX_QUEUE_0		0
@@ -1162,6 +1221,59 @@
 		MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
 
 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
+#define GT64260_ETH_IGMP_CAPTURE_ENABLE			0
+#define GT64260_ETH_IGMP_CAPTURE_DISABLE		(1<<0)
+#define GT64260_ETH_BPDU_PACKETS_AS_NORMAL		0
+#define GT64260_ETH_BPDU_PACKETS_TO_RX_QUEUE		(1<<1)
+#define GT64260_ETH_PARTITION_DISABLE			0
+#define GT64260_ETH_PARTITION_ENABLE			(1<<2)
+#define GT64260_ETH_PARTITION_DISABLE			0
+#define GT64260_ETH_TX_PRIORITY_1_HIGH_1_LOW		0
+#define GT64260_ETH_TX_PRIORITY_2_HIGH_1_LOW		(0x1<<3)
+#define GT64260_ETH_TX_PRIORITY_4_HIGH_1_LOW		(0x2<<3)
+#define GT64260_ETH_TX_PRIORITY_6_HIGH_1_LOW		(0x3<<3)
+#define GT64260_ETH_TX_PRIORITY_8_HIGH_1_LOW		(0x4<<3)
+#define GT64260_ETH_TX_PRIORITY_10_HIGH_1_LOW		(0x5<<3)
+#define GT64260_ETH_TX_PRIORITY_12_HIGH_1_LOW		(0x6<<3)
+#define GT64260_ETH_TX_PRIORITY_ALL_HIGH_0_LOW		(0x7<<3)
+#define GT64260_ETH_TX_PRIORITY_MASK			(0x7<<3)
+#define GT64260_ETH_RX_PRIORITY_LOWEST			0
+#define GT64260_ETH_RX_PRIORITY_HIGHEST			(0x3<<6)
+#define GT64260_ETH_RX_PRIORITY_OVERRIDE_DISABLE	0
+#define GT64260_ETH_RX_PRIORITY_OVERRIDE_ENABLE		(1<<8)
+#define GT64260_ETH_ENABLE_AUTO_NEG_FOR_DPLX		0
+#define GT64260_ETH_DISABLE_AUTO_NEG_FOR_DPLX		(1<<9)
+#define GT64260_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL	0
+#define GT64260_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	(1<<10)
+#define GT64260_ETH_FORCE_LINK_PASS			0
+#define GT64260_ETH_DO_NOT_FORCE_LINK_PASS		(1<<11)
+#define GT64260_ETH_DISABLE_FLOW_CTRL			0
+#define GT64260_ETH_ENABLE_FLOW_CTRL			(1<<12)
+/* Bit 13 is reserved. */
+#define GT64260_ETH_MAX_RX_PACKET_1518BYTE		0
+#define GT64260_ETH_MAX_RX_PACKET_1536BYTE		(0x1<<14)
+#define GT64260_ETH_MAX_RX_PACKET_2048BYTE		(0x2<<14)
+#define GT64260_ETH_MAX_RX_PACKET_64KBYTE		(0x3<<14)
+#define GT64260_ETH_MAX_RX_PACKET_MASK			(0x7<<14)
+#define GT64260_ETH_CLR_MIB_COUNTERS			0
+/* Bit 17 is undocumented. */
+#define GT64260_ETH_SET_SPEED_TO_10			0
+#define GT64260_ETH_SET_SPEED_TO_100			(1<<18)
+#define GT64260_ETH_ENABLE_AUTONEG_FOR_SPEED		0
+#define GT64260_ETH_DISABLE_AUTONEG_FOR_SPEED		(1<<19)
+#define GT64260_ETH_ENABLE_MII				0
+#define GT64260_ETH_ENABLE_RMII				(1<<20)
+#define GT64260_ETH_DISABLE_DSCP			0
+#define GT64260_ETH_ENABLE_DSCP				(1<<21)
+/* Bits 22 - 31 are reserved. */
+
+#define	GT64260_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE		\
+		GT64260_ETH_RX_PRIORITY_OVERRIDE_ENABLE	|	\
+		GT64260_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |	\
+		GT64260_ETH_DO_NOT_FORCE_LINK_PASS	|	\
+		GT64260_ETH_MAX_RX_PACKET_1536BYTE	|	\
+		GT64260_ETH_ENABLE_RMII
+
 #define MV643XX_ETH_CLASSIFY_EN				(1<<0)
 #define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL		0
 #define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7	(1<<1)
@@ -1173,6 +1285,23 @@
 		MV643XX_ETH_PARTITION_DISABLE
 
 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
+#define GT64260_ETH_RETRANSMIT_COUNT_MASK		(0xf<<2)
+#define GT64260_ETH_BLM_RX_NO_SWAP			0
+#define GT64260_ETH_BLM_RX_BYTE_SWAP			(1<<6)
+#define GT64260_ETH_BLM_TX_NO_SWAP			0
+#define GT64260_ETH_BLM_TX_BYTE_SWAP			(1<<7)
+#define GT64260_ETH_PCI_OVERRIDE			(1<<8)
+#define GT64260_ETH_RIFB				(1<<9)
+#define GT64260_ETH_BURST_SIZE_1_64BIT			(0x0<<12)
+#define GT64260_ETH_BURST_SIZE_2_64BIT			(0x1<<12)
+#define GT64260_ETH_BURST_SIZE_4_64BIT			(0x2<<12)
+#define GT64260_ETH_BURST_SIZE_8_64BIT			(0x3<<12)
+
+#define	GT64260_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE		\
+		GT64260_ETH_RETRANSMIT_COUNT_MASK	|	\
+		GT64260_ETH_RIFB			|	\
+		GT64260_ETH_BURST_SIZE_4_64BIT
+
 #define MV643XX_ETH_RIFB			(1<<0)
 #define MV643XX_ETH_RX_BURST_SIZE_1_64BIT		0
 #define MV643XX_ETH_RX_BURST_SIZE_2_64BIT		(1<<1)
@@ -1198,6 +1327,13 @@
 		MV643XX_ETH_IPG_INT_RX(0)		|	\
 		MV643XX_ETH_TX_BURST_SIZE_4_64BIT
 
+/* These macros describe Ethernet Port Sdma command reg (SDCMR) bits */
+#define GT64260_ETH_ENABLE_RX_DMA			(1<<7)
+#define GT64260_ETH_ABORT_RX_DMA			(1<<15)
+#define GT64260_ETH_START_TX_HIGH			(1<<23)
+#define GT64260_ETH_START_TX_LOW			(1<<24)
+#define GT64260_ETH_ABORT_TX_DMA			(1<<31)
+
 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
 #define MV643XX_ETH_SERIAL_PORT_DISABLE			0
 #define MV643XX_ETH_SERIAL_PORT_ENABLE			(1<<0)
@@ -1279,7 +1417,10 @@
 #define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY		(1<<10)
 /* PSR bits 11-31 are reserved */
 
+/* Default TX ring size is 800 descriptors */
 #define	MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE	800
+
+/* Default RX ring size is 400 descriptors */
 #define	MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE	400
 
 #define MV643XX_ETH_DESC_SIZE				64