Subject: Re: [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count overflow

From: Sean Anderson <[email-masked]>
Date: Thu, 5 Sep 2024 10:55:49 -0400

On 9/4/24 13:19, Pandey, Radhey Shyam wrote:
>> -----Original Message-----
>> From: Sean Anderson <[email-masked]>
>> Sent: Tuesday, September 3, 2024 11:31 PM
>> To: Pandey, Radhey Shyam <[email-masked]>; David S .
>> Miller <[email-masked]>; Eric Dumazet <[email-masked]>;
>> Jakub Kicinski <[email-masked]>; Paolo Abeni <[email-masked]>;
>> [email-masked]
>> Cc: Simek, Michal <[email-masked]>; linux-arm-
>> [email-masked]; Ariane Keller <[email-masked]>;
>> [email-masked]; Daniel Borkmann <[email-masked]>;
>> Andy Chiu <[email-masked]>; Sean Anderson
>> <[email-masked]>
>> Subject: [PATCH net] net: xilinx: axienet: Fix IRQ coalescing packet count
>> overflow
>> 
>> If coalesce_count is greater than 255 it will not fit in the register and
>> will overflow. Clamp it to 255 for more-predictable results.
>> 
>> Signed-off-by: Sean Anderson <[email-masked]>
>> Fixes: 8a3b7a252dca ("drivers/net/ethernet/xilinx: added Xilinx AXI Ethernet
>> driver")
>> ---
>> 
>>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
>> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
>> index 9aeb7b9f3ae4..5f27fc1c4375 100644
>> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
>> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
>> @@ -252,7 +252,8 @@ static u32 axienet_usec_to_timer(struct axienet_local
>> *lp, u32 coalesce_usec)
>>  static void axienet_dma_start(struct axienet_local *lp)
>>  {
>>  	/* Start updating the Rx channel control register */
>> -	lp->rx_dma_cr = (lp->coalesce_count_rx <<
>> XAXIDMA_COALESCE_SHIFT) |
>> +	lp->rx_dma_cr = (min(lp->coalesce_count_rx, 255) <<
>> +			 XAXIDMA_COALESCE_SHIFT) |
>>  			XAXIDMA_IRQ_IOC_MASK |
> 
> Instead of every time clamping coalesce_count_rx on read I think better 
> to do it place where it set in axienet_ethtools_set_coalesce()? It would
> also represent the coalesce count state that is reported by get_coalesce()
> and same is being used in programming.

The parameter which will be trickier is the timer, which is also clamped
but depends on the (DMA) clock speed. So theoretically it may be
different if the clock gets changed at runtime between when we set
coalesce and when we apply it. But do we even support dynamic rate
changes for that clock?

In either case, I think this will be easier to do as part of [1], since I
am already rearranging the calculation in that patch.

--Sean

[1] https://lore.kernel.org/netdev/[email-masked]/

>> XAXIDMA_IRQ_ERROR_MASK;
>>  	/* Only set interrupt delay timer if not generating an interrupt on
>>  	 * the first RX packet. Otherwise leave at 0 to disable delay interrupt.
>> @@ -264,7 +265,8 @@ static void axienet_dma_start(struct axienet_local
>> *lp)
>>  	axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, lp->rx_dma_cr);
>> 
>>  	/* Start updating the Tx channel control register */
>> -	lp->tx_dma_cr = (lp->coalesce_count_tx <<
>> XAXIDMA_COALESCE_SHIFT) |
>> +	lp->tx_dma_cr = (min(lp->coalesce_count_tx, 255) <<
>> +			 XAXIDMA_COALESCE_SHIFT) |
>>  			XAXIDMA_IRQ_IOC_MASK |
>> XAXIDMA_IRQ_ERROR_MASK;
>>  	/* Only set interrupt delay timer if not generating an interrupt on
>>  	 * the first TX packet. Otherwise leave at 0 to disable delay interrupt.
>> --
>> 2.35.1.1320.gc452695387.dirty
>