Subject: Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations

From: "H. Peter Anvin" <[email-masked]>
Date: Wed, 22 Aug 2012 08:13:41 -0700

On 08/22/2012 07:58 AM, Ben Hutchings wrote:
>
> Because reordering, and see the comment at the top of this file.
>

Your architecture sounds similar to one I once worked on (Orion 
Microsystems CNIC/OPA-2).  That architecture had a descriptor ring in 
device memory, and a single trigger bit would move the head pointer.

We used write combining to write out a set of descriptors, and then used 
a non-write-combining write to do the final write which bumps the head 
pointer.  The UC write flushes the write combiners ahead of it, so it 
ends up with two transactions (one for the WC data and one for the UC 
trigger) but it could frequently push quite a few descriptors in that 
operation.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.