Subject: Re: [PATCH] net/cpsw: don't disable_irqs() after an interrupt has been received.

From: Sebastian Andrzej Siewior <[email-masked]>
Date: Wed, 17 Apr 2013 23:12:54 +0200

On 04/17/2013 12:08 PM, Mugunthan V N wrote:
> Mine shows [    0.000000] AM335X ES2.0 (neon )
> 
> In Beagle bone (silicon revision 1.0) there is a bug in CPSW irq in
> Silicon, please refer
> http://www.ti.com/lit/er/sprz360e/sprz360e.pdf  Advisory 1.0.9
> 
> Beagle bone black has Silicon revision 2.0 where the bug is fixed and
> you are able
> to test it properly and it hangs in my bone black as the IRQ is properly
> connected
> to A8

Are you there is not something else going on? According to the TRM
14.3.1.3.1 + .14.3.1.3.2 the interrupts are properly disabled. So
according to the TRM, the interrupts should not be disabled and not
appear anymore.
Advisory 1.0.9 says that only TXPEND[0] and RXPEND[0] are connected to
the INTC rather than TXPEND[0-7] (+RXPEND) and therefore only channel 0
can be used. That means I have still no idea why the interrupt is not
cleared on your ES2.0.

> Regards
> Mugunthan V N

Sebastian