Subject: Re: net/macb: clear tx/rx completion flags in ISR

From: Hein Tibosch <[email-masked]>
Date: Fri, 19 Apr 2013 13:13:26 +0800

Hi Steffen,

> At least in the cadence IP core on the Xilinx Zynq SoC the TCOMP/RCOMP flags
> are not auto-cleaned. As these flags are evaluated, they need to be cleaned.

This patch does not work for at least the AVR32 platform. Both RCOMP/RCOMP
are cleared by *reading* the ISR and writing them would be fatal.

Could you tell me the version of the macb of Xilinx Zynq?

    u32 version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
            | MACB_GREGS_VERSION;

On an AP7000 it reads as 0x0000010D

I am thinking of making a patch like:

    if (bp->version >= xxx)
        macb_writel(bp, ISR, MACB_BIT(TCOMP));

    if (bp->version >= xxx)
        macb_writel(bp, ISR, MACB_BIT(RCOMP));

which would make it work on both platforms.

Hein