Subject: Re: [PATCH v2] sh_eth: use RNC mode for R8A7790/R87791

From: Sergei Shtylyov <[email-masked]>
Date: Tue, 03 Jun 2014 01:17:31 +0400

Hello.

On 06/03/2014 01:05 AM, David Miller wrote:

>>>>      Looks like the early SH2/3 SoCs didn't implement the whole register.
>>>> Despite that, sh_eth_dev_init() always writes to this register... :-/
>>>> So far, the RMCR.RNC bit was mostly set for the Gigabit-capable
>>>> controllers, however that rule wasn't strictly followed. Well, this
>>>> driver is still a mess, and it's hard to deal with it without the
>>>> necessary documentation.

>>> Why don't we therefore:

>>> 1) Skip the register write if the per-chip value is zero.

>>     I rather thought about not writing when the register is not
>>     implemented.
>> I'll probably look into this when I have time.

>>> 2) Add the RNC bit to all of the gigabit capable controllers.

>>     I probably misspoke -- all the Gigabit controllers already have it
>>     set, it's just that some 100 MBbps ones have it set, but most don't.

> So these chips that do not implement the register, they only process
> one RX descriptor at a time until the interrupt handler re-enables
> DMA receive?

    I just don't know. Looks like the driver is broken on SH2/3 even more than 
I thought: it always reads the EDRRR register in sh_eth_rx() trying to 
understand if the reception has been stopped but that register doesn't seem to 
exist on SH2/3. Moreover, sh_eth_interrupt() reads EESR in order to determine 
the interrupt status but that register doesn't seem to exist on SH2/3 either!

WBR, Sergei