From: Mugunthan V N <mugunthanvnm@ti•com>
To: John Ogness <john.ogness@linutronix•de>, <linux-kernel@vger•kernel.org>
Cc: <davem@davemloft•net>, <balbi@ti•com>, <george.cherian@ti•com>,
<jhovold@gmail•com>, <mpa@pengutronix•de>,
<bhutchings@solarflare•com>, <zonque@gmail•com>,
<tklauser@distanz•ch>, <netdev@vger•kernel.org>
Subject: Re: [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset
Date: Fri, 14 Nov 2014 23:53:36 +0530 [thread overview]
Message-ID: <546648A8.1000102@ti.com> (raw)
In-Reply-To: <87sihlj11v.fsf@linutronix.de>
On Friday 14 November 2014 08:12 PM, John Ogness wrote:
> The TX_IN_SEL offset for the CPSW_PORT/TX_IN_CTL register was
> incorrect. This caused the Dual MAC mode to never get set when
> it should. It also caused possible unintentional setting of a
> bit in the CPSW_PORT/TX_BLKS_REM register.
>
> The purpose of setting the Dual MAC mode for this register is to:
>
> "... allow packets from both ethernet ports to be written into
> the FIFO without one port starving the other port."
> - AM335x ARM TRM
>
> Signed-off-by: John Ogness <john.ogness@linutronix•de>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti•com>
Regards
Mugunthan V N
next prev parent reply other threads:[~2014-11-14 18:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-14 14:42 [PATCH 1/1] drivers: net: cpsw: Fix TX_IN_SEL offset John Ogness
2014-11-14 18:23 ` Mugunthan V N [this message]
2014-11-16 19:20 ` David Miller
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