Subject: Re: [PATCH 2/4] net: phy: at803x: Allow specifying the RGMII RX clock delay via phy mode

From: Mason <[email-masked]>
Date: Sun, 27 Dec 2015 21:22:48 +0100

On 27/12/2015 04:28, Florian Fainelli wrote:

> Le 25/12/2015 16:27, Martin Blumenstingl wrote:
>
>> diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c
>> index f566b6e..0b262a2 100644
>> --- a/drivers/net/phy/at803x.c
>> +++ b/drivers/net/phy/at803x.c
>> @@ -36,8 +36,10 @@
>>  #define AT803X_INSR				0x0013
>>  #define AT803X_DEBUG_ADDR			0x1D
>>  #define AT803X_DEBUG_DATA			0x1E
>> -#define AT803X_DEBUG_SYSTEM_MODE_CTRL		0x05
>> -#define AT803X_DEBUG_RGMII_TX_CLK_DLY		BIT(8)
>> +#define AT803X_DEBUG_REG_0			0x00
> 
> Seems like the previous register name might have been clearer that the
> new name you suggest here, did that come from a different GPL tarball or
> documentation?

http://www.redeszone.net/app/uploads/2014/04/AR8035.pdf

According to the 8035 data sheet, the debug register at offset 0
is just "Debug register 0". In fact, the only non-reserved bit is
"rgmii rx clock delay enable/disable"

So the SYSTEM_MODE_CTRL name is misleading. Unless the register
has different semantics on the other PHYs?

Regards.