Subject: Re: [BUG] mv88e6xxx: tx regression in v5.3

From: Baruch Siach <[email-masked]>
Date: Sun, 15 Dec 2019 12:13:25 +0200

Hi Marek,

On Thu, Dec 12 2019, Marek Behun wrote:

> On Thu, 12 Dec 2019 20:31:29 +0100
> Andrew Lunn <[email-masked]> wrote:
>
>> > diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> > index bd881497b872..8f61cae9d3b0 100644
>> > --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> > +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
>> > @@ -408,6 +408,11 @@ port@5 {
>> >  				reg = <5>;
>> >  				label = "cpu";
>> >  				ethernet = <&cp1_eth2>;
>> > +
>> > +				fixed-link {
>> > +					speed = <2500>;
>> > +					full-duplex;
>> > +				};
>> >  			};
>> >  		};
>>
>> The DSA driver is expected to configure the CPU port at its maximum
>> speed. You should only add a fixed link if you need to slow it down.
>> I expect 2500 is the maximum speed of this port.
>
> Baruch, if the cpu port is in 2500 base-x, remove the fixed-link and do
> this:
>
> port@5 {
> 	reg = <5>;
> 	label = "cpu";
> 	ethernet = <&cp1_eth2>;
> 	phy-mode = "2500base-x";
> 	managed = "in-band-status";
> };

Thanks. That is enough to fix the phylink issue triggered by commit
7fb5a711545 ("net: dsa: mv88e6xxx: drop adjust_link to enabled
phylink").

The Clearfog GT-8K DT has also this on the cpu side:

&cp1_eth2 {
        status = "okay";
        phy-mode = "2500base-x";
        phys = <&cp1_comphy5 2>;
        fixed-link {
                speed = <2500>;
                full-duplex;
        };
};

Should I drop fixed-link here as well?

The call to mv88e6341_port_set_cmode() introduced in commit 7a3007d22e8
("net: dsa: mv88e6xxx: fully support SERDES on Topaz family") still
breaks port 5 (cpu) configuration. When called, its mode parameter is
set to PHY_INTERFACE_MODE_2500BASEX (19).

Any idea?

Thanks,
baruch

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