From: Andrew Lunn <andrew@lunn•ch>
To: Jiawen Wu <jiawenwu@trustnetic•com>
Cc: netdev@vger•kernel.org, mengyuanlou@net-swift•com
Subject: Re: [PATCH net-next v3 2/3] net: txgbe: Reset hardware
Date: Tue, 11 Oct 2022 03:55:05 +0200 [thread overview]
Message-ID: <Y0TM+eHBtGa0YLXq@lunn.ch> (raw)
In-Reply-To: <00f601d8dc71$f0ded460$d29c7d20$@trustnetic.com>
> > So you have an IO barrier before and a read barrier afterwards. So all i think you need is a
> mb(), not a
> > full rd32().
> >
> > Andrew
> >
>
> I think we need a readl(), because there are problems that sometimes IO is not synchronized with
> flushing memory on some domestic cpu platforms.
> It can become a serious problem, causing register error configurations.
So please document this as a comment in the code.
I also then start to wounder if more such flushes are needed, to
handle this broken hardware. Do you have a detailed description of
what actually goes wrong? Otherwise how do you know when such a flush
is needed?
Andrew
next prev parent reply other threads:[~2022-10-11 1:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-29 9:34 [PATCH net-next v3 0/3] net: WangXun txgbe ethernet driver Jiawen Wu
2022-09-29 9:34 ` [PATCH net-next v3 1/3] net: txgbe: Store PCI info Jiawen Wu
2022-09-29 9:34 ` [PATCH net-next v3 2/3] net: txgbe: Reset hardware Jiawen Wu
2022-09-29 16:46 ` Andrew Lunn
2022-10-10 6:31 ` Jiawen Wu
2022-10-11 1:55 ` Andrew Lunn [this message]
2022-10-11 6:02 ` Jiawen Wu
2022-09-29 9:34 ` [PATCH net-next v3 3/3] net: txgbe: Set MAC address and register netdev Jiawen Wu
2022-09-29 17:09 ` Andrew Lunn
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