Subject: Re: [PATCH net-next 2/2] net: mdio: add amlogic gxl mdio mux support

From: Andrew Lunn <[email-masked]>
Date: Wed, 18 Jan 2023 04:02:43 +0100

> +static int gxl_enable_internal_mdio(struct gxl_mdio_mux *priv)
> +{
> +	u32 val;
> +
> + 	/* Setup the internal phy */
> +	val = (REG3_ENH |
> +	       FIELD_PREP(REG3_CFGMODE, 0x7) |
> +	       REG3_AUTOMDIX |
> +	       FIELD_PREP(REG3_PHYADDR, 8) |
> +	       REG3_LEDPOL |
> +	       REG3_PHYMDI |
> +	       REG3_CLKINEN |
> +	       REG3_PHYIP);
> +
> +	writel_relaxed(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4);
> +	writel_relaxed(val, priv->regs + ETH_REG3);
> +	mdelay(10);

Probably the second _relaxed() should not be. You want it guaranteed
to be written out before you do the mdelay().

> +
> +	/* Set the internal phy id */
> +	writel_relaxed(FIELD_PREP(REG2_PHYID, 0x110181),
> +		       priv->regs + ETH_REG2);

So how does this play with what Heiner has been reporting recently?
What is the reset default? Who determined this value?

> +	/* Enable the internal phy */
> +	val |= REG3_PHYEN;
> +	writel_relaxed(val, priv->regs + ETH_REG3);
> +	writel_relaxed(0, priv->regs + ETH_REG4);
> +
> +	/* The phy needs a bit of time to come up */
> +	mdelay(10);

What do you mean by 'come up'? Not link up i assume. But maybe it will
not respond to MDIO requests?

    Andrew