Subject: Re: [PATCH net 1/3] net: mediatek: sgmii: ensure the SGMII PHY is powered down on configuration

From: "Russell King (Oracle)" <[email-masked]>
Date: Thu, 19 Jan 2023 17:17:47 +0000

On Thu, Jan 19, 2023 at 06:12:46PM +0100, Bjørn Mork wrote:
> From: Alexander Couzens <[email-masked]>
> 
> The code expect the PHY to be in power down which is only true after reset.
> Allow changes of the SGMII parameters more than once.
> 
> There are cases when the SGMII_PHYA_PWD register contains 0x9 which
> prevents SGMII from working. The SGMII still shows link but no traffic
> can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
> taken from a good working state of the SGMII interface.
> 
> Signed-off-by: Alexander Couzens <[email-masked]>
> [ bmork: rebased and squashed into one patch ]
> Signed-off-by: Bjørn Mork <[email-masked]>
> ---
>  drivers/net/ethernet/mediatek/mtk_sgmii.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c
> index 5c286f2c9418..481f2f1e39f5 100644
> --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
> +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
> @@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
>  		bmcr = 0;
>  	}
>  
> +	/* PHYA power down */
> +	regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
> +			   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
> +

Doing this unconditionally means that the link will drop - even when
we aren't doing any reconfiguration (except changing the advertisement).
That's why I made it conditional in the version of the patch I sent
(which failed due to the unknown bits 3 and 0.)

We should always avoid bouncing the link when there's no reason to.

-- 
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