Subject: Re: [PATCH] r8169: introduce polling method for link change

From: Andrew Lunn <[email-masked]>
Date: Mon, 7 Jun 2021 14:49:46 +0200

On Mon, Jun 07, 2021 at 12:32:29PM +0000, David Laight wrote:
> From: Koba Ko
> > Sent: 07 June 2021 05:35
> ...
> > After consulting with REALTEK, I can identify RTL8106e by PCI_VENDOR
> > REALTEK, DEVICE 0x8136, Revision 0x7.
> > I would like to make PHY_POLL as default for RTL8106E on V2.
> > because there's no side effects besides the cpu usage rate would be a
> > little higher,
> > How do you think?
> 
> If reading the PHY registers involves a software bit-bang
> of an MII register (rather than, say, a sleep for interrupt
> while the MAC unit does the bit-bang) then you can clobber
> interrupt latency because of all the time spent spinning.

That is not what PHY IRQ/POLL means in the PHY subsystem.

Many PHYs don't actually have there interrupt output connected to a
GPIO. This is partially because 803.2 C22 and C45 standards don't
define interrupts. Each vendor which supports interrupts uses
proprietary registers. So by default, the PHY subsystem will poll the
status of the PHY once per second to see if the link has changed
state. If the combination of PHY hardware, board hardware and PHY
driver does have interrupts, the PHY subsystem will not poll, but wait
for an interrupt, and then check the status of the link.

As for MII bus masters, i only know of one which is interrupt driven,
rather than polled IO, for completion. The hardware is clocking out 64
bits at 2.5MHz. So it is done rather quickly. I profiled that one
using interrupts, and the overhead of dealing with the interrupt is
bigger than polling.

    Andrew